Half-adder in VHDL

Yay. My first code in VHDL.

library ieee;
use ieee.std_logic_1164.all;

entity ha_CG is
Port ( X : in std_logic;
Y : in std_logic;
Sum : out std_logic;
Carry : out std_logic);
end ha_CG;

architecture Behavioral of ha_CG is
begin
Sum <= X xor Y;
Carry <= X and Y;
end Behavioral;

Happy enough to successfully compile it with GHDL and Wine.

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