Functional and Timing Simulation in VHDL

Functional Simulation:

  1. Create New Project
  2. Create New VHDL file, add to the project
  3. Create Vector Waveform file, by selecting File> New, save the file
  4. Edit> End Time, enter 200ns
  5. View> Fit in Window
  6. Edit> Insert Node or Bus, add names of signal (pin) to be observed or use Node Finder and set Pins: all
  7. Set the input pins by highlighting the area and assign logic values
  8. Assignment>Settings, click Simulator, choose Functional as the simulation mode
  9. Before running the simulation, select Processing> Generate Functional Simulation Netlist
  10. Run the simulation by Processing> Start Simulation

Timing Simulation:
Same as above steps, except step
8. Assignment>Settings, click Simulator, choose Timing as the simulation mode