## Hybrid multipliers

Have read this, and these are several notes:

1. Hybrid multiplier is application of bit parallel architectures to arithmetic in the subfield $GF(2^n)$ and of a bit serial structures to arithmetic in the extension field $GF((2^n)^m)$
2. The major advantage of hybrid architecture is that the number clock cycles for one multiplication is reduced by a factor of $n$. The hybrid multiplier explores thus the time-space trade-off paradigm, where the degree of the trade-off (performance versus complexity) is determined by the field decomposition $n\cdot m$