A simple lookup table in vhdl


library ieee;
use ieee.std_logic_1164.all;

entity simplelutCG is
port
(
clk : in std_logic;
e : in std_logic;
r : in std_logic;
data : out std_logic_vector(3 downto 0)
);
end entity simplelutCG;

architecture behavioral of simplelutCG is
signal i : integer range 0 to 3:=0; -- change the range value
signal enable : std_logic:='0';
type lut is array ( 0 to 2**2 - 1) of std_logic_vector(3 downto 0);
constant my_lut : lut := (
0 => "0000",
1 => "0001",
2 => "0010",
3 => "0011");

begin
process (e)
begin
signal
if e'event and e = '1' then
enable <= '1';
end if;
end process;

process (clk)
begin
if rising_edge (clk) then
if (enable = '1') then
data <= my_lut(3);
end case;
end if;
end process;

end architecture behavioral;

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