Updates from October, 2010 Toggle Comment Threads | Keyboard Shortcuts

  • CG 9:55 pm on October 29, 2010 Permalink | Reply
    Tags: , , , ,   

    Tristate buffer 


    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;

    ENTITY bidir IS
    PORT(
    bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
    oe, clk : IN STD_LOGIC;
    inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    outp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
    END bidir;

    ARCHITECTURE maxpld OF bidir IS
    SIGNAL a : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores
    -- value from input.
    SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores
    BEGIN -- feedback value.
    PROCESS(clk)
    BEGIN
    IF clk = '1' AND clk'EVENT THEN -- Creates the flipflops
    a <= inp;
    outp <= b;
    END IF;
    END PROCESS;
    PROCESS (oe, bidir) -- Behavioral representation
    BEGIN -- of tri-states.
    IF( oe = '0') THEN
    bidir <= "ZZZZZZZZ";
    b <= bidir;
    ELSE
    bidir <= a;
    b <= bidir;
    END IF;
    END PROCESS;
    END maxpld;

     

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    • Budi Rahardjo 12:11 am on October 30, 2010 Permalink | Reply

      Ok I can see that the tri-state is happening. Try this approach with your design and see if it can utilize tri-state in sharing the look-up table.

      • CG 5:51 am on October 30, 2010 Permalink | Reply

        haih, bikin tri-state aja susah gini ya 😀

  • CG 2:30 pm on October 21, 2010 Permalink | Reply
    Tags: , , , , register,   

    Adder with register 


    library ieee;
    use ieee.std_logic_1164.all;

    entity adder2bitwithregjuga is
    port
    (clock: in std_logic;
    Ain: in std_logic;
    Bin: in std_logic;
    shift: in std_logic;
    CI: in std_logic;
    S : out std_logic_vector(1 downto 0);
    C0: out std_logic);
    end adder2bitwithregjuga;

    architecture arch of adder2bitwithregjuga is
    -- Specify the Full Adder subcircuit
    component Full_Adder
    port
    (AI,BI,CYI: in std_logic;
    SUM, CYO :out std_logic);
    end component;

    --Reserve a few signals for internal connections
    --signal CY0, CY1, CY2: bit;
    signal flag: std_logic;
    signal CY0: std_logic;
    signal A,B : std_logic_vector(1 downto 0);
    begin
    FA0: Full_Adder port map (A(0), B(0), CI, S(0), CY0);
    FA1: Full_Adder port map (A(1), B(1), CY0, S(1), C0);
    process(clock)
    begin
    flag <= clock and shift;
    if rising_edge(flag) then
    A(1) <= A(0);
    A(0) <= Ain;
    B(1) <= B(0);
    B(0) <= Bin;
    end if;
    end process;

    end arch;

    entity Full_Adder is
    port
    (AI,BI,CYI: in bit;
    SUM, CYO : out bit);
    end Full_Adder;

    architecture FA of Full_Adder is
    component Half_Adder
    port
    (W,X: in bit;
    Y,Z: out bit);
    end component;
    signal Y0,Z0,Z1: bit;
    begin
    HA0: Half_Adder port map(AI, BI, Y0, Z0);
    HA1: Half_Adder port map(CYI, Y0, SUM, Z1);
    CYO <= Z0 or Z1;
    end FA;

    entity Half_Adder is
    port
    (W,X: in bit;
    Y,Z: out bit);
    end Half_Adder;

    architecture HA of Half_Adder is
    begin
    Y <= W xor X; -- This is the sum bit
    Z <= W and X; -- This is the carry bit
    end HA;

     
    • Bobby 4:46 pm on October 21, 2010 Permalink | Reply

      HORRROOOORRR

    • Budi Rahardjo 2:03 pm on October 23, 2010 Permalink | Reply

      liat tuh di kodenya sampe ada yang ketawa (smiley)… he he he

      • CG 6:38 pm on October 23, 2010 Permalink | Reply

        itu bukan smile tapi lagi teriak “HORRROOOORRR! ” hihihihihi

  • CG 10:56 am on October 18, 2010 Permalink | Reply
    Tags: Distraction   

    If Facebook existed years ago 

    This is brilliant, and very funny 🙂 another great way to learn about history 😀

    1. http://www.facebook.com/note.php?note_id=474454177124&id=639850213
    2. http://coolmaterial.com/roundup/if-historical-events-had-facebook-statuses-part-2/
     
    • mer 2:28 pm on November 19, 2010 Permalink | Reply

      hahaha…. brilliantly funny indeed.

  • CG 5:52 pm on October 16, 2010 Permalink | Reply
    Tags: , kids, , scratch   

    Scratch – Programming for Kids 

    wow, this is fun. Scratch, is brilliant. This is what cadets have been doing the last 2 days 😀

     
    • tkmaia 11:31 am on October 17, 2010 Permalink | Reply

      yayyy!

      • CG 5:45 am on October 18, 2010 Permalink | Reply

        wow, comment bu tkmaia baru masuk, kena filter spam 🙂

  • CG 6:50 pm on October 13, 2010 Permalink | Reply
    Tags: , , , linux,   

    Compiling assembly on Linux (Ubuntu on Virtual Box) 

    gcc -S logical.c

    gcc -O1 -S logical.c

    gcc -O2 -S logical.c

    objdump -d logical.o

     
  • CG 12:09 pm on October 13, 2010 Permalink | Reply
    Tags: , , , waveform   

    13bit adder 

    Don’t laugh. I’m still doing this and I want to make sure this is documented and can be easily use later for reference.


    library ieee;
    use ieee.std_logic_1164.all;

    entity adder13bit is
    port (clock, Ain, Bin : in std_logic;
    Aout, Bout, Cout : out std_logic;
    shift_in: in std_logic);
    end entity adder13bit;

    architecture rtl of adder13bit is
    signal flag: std_logic;
    signal a, b, c: std_logic_vector(12 downto 0);
    begin
    process(clock)
    begin
    flag <= clock and shift_in;
    if rising_edge(flag) then
    Aout <= a(12);
    Bout <= b(12);
    for N in 12 downto 1 loop
    a(N) <= A(N-1);
    b(N) <= B(N-1);
    end loop;
    a(0) <= Ain;
    b(0) <= Bin;
    end if;

    for N in 12 downto 0 loop
    c(N) <= A(N) xor B(N);
    Cout <= c(N);
    end loop;
    end process;
    end architecture rtl;

     
    • Budi Rahardjo 4:41 am on October 14, 2010 Permalink | Reply

      Good. Tapi formating program VHDL nya kok kacau. WordPress gak support VHDL?

      • CG 2:48 pm on October 14, 2010 Permalink | Reply

        iya gak support. kalau lyx sih support VHDL, yay 🙂

  • CG 6:53 pm on October 12, 2010 Permalink | Reply
    Tags: computer architectures, ,   

    Registers in Snow Leopard 64-bit 

    Snow Leopard has different architecture and different register names.


    [image taken from http://www.sealiesoftware.com/blog/archive/2008/09/22/objc_explain_So_you_crashed_in_objc_msgSend.html%5D

     
  • CG 3:39 pm on October 12, 2010 Permalink | Reply
    Tags: , , , , mac os x,   

    Compiling assembly on Snow Leopard 

    Comparing the compiling result with compiling assembly with Leopard (Mac OS X 10.5)

    code in c

    int logical(int x, int y){
       int t1 = x^y;
       int t2 = t1 >> 17;
       int mask = (1<<13)-7;
       int rval = t2 & mask;
       return rval;
    }
    

    gcc -S logical.c

    gcc -O1 -S logical.c

    gcc -O2 -S logical.c

    dumping object file
    gcc -c logical.c
    otool -tv logical.o

     
  • CG 11:02 pm on October 10, 2010 Permalink | Reply
    Tags: generating clock, , ,   

    Generating clock in quartus 

    After spending days finding answers on how to generate clock in quartus, I finally found the answer here:

    This is very easy. That’s why people always say RTFM.

    But later I still want to try this:

    1. http://www.stefanvhdl.com/vhdl/html/clk_rst.html
    2. http://www.doulos.com/knowhow/vhdl_designers_guide/tips/clock_generation/
    3. http://www.excamera.com/articles/23/clock.html
    4. http://www.edaboard.com/thread132686.html
     
  • CG 1:19 pm on October 8, 2010 Permalink | Reply
    Tags: link,   

    Complete Blog in VHDL 

    Complete Blog in VHDL : http://vhdl4u.blogspot.com/

     
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