Shift-register 299-bit

The previous problem about 299-xor seemed to be related to port using. big number of ports cannot be declared in parallel.

Today I learned to design a shift register that fits. Thank you, Guru 🙂


library ieee;
use ieee.std_logic_1164.all;

entity regs is
port (clock, Ain, Bin : in std_logic;
Aout, Bout, Cout : out std_logic;
shift_in: in std_logic);

end entity regs;

architecture rtl of regs is
signal flag: std_logic;
signal a, b, c: std_logic_vector(298 downto 0);
begin
process(clock)
begin
flag <= clock and shift_in;
if rising_edge(flag) then
Aout <= a(298);
Bout <= b(298);
for N in 298 downto 1 loop
a(N) <= A(N-1);
b(N) <= B(N-1);
end loop;
a(0) <= Ain;
b(0) <= Bin;
end if;
end process;
end architecture rtl;

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