13bit adder

Don’t laugh. I’m still doing this and I want to make sure this is documented and can be easily use later for reference.

library ieee;
use ieee.std_logic_1164.all;

entity adder13bit is
port (clock, Ain, Bin : in std_logic;
Aout, Bout, Cout : out std_logic;
shift_in: in std_logic);
end entity adder13bit;

architecture rtl of adder13bit is
signal flag: std_logic;
signal a, b, c: std_logic_vector(12 downto 0);
flag <= clock and shift_in;
if rising_edge(flag) then
Aout <= a(12);
Bout <= b(12);
for N in 12 downto 1 loop
a(N) <= A(N-1);
b(N) <= B(N-1);
end loop;
a(0) <= Ain;
b(0) <= Bin;
end if;

for N in 12 downto 0 loop
c(N) <= A(N) xor B(N);
Cout <= c(N);
end loop;
end process;
end architecture rtl;