Adder with register


library ieee;
use ieee.std_logic_1164.all;

entity adder2bitwithregjuga is
port
(clock: in std_logic;
Ain: in std_logic;
Bin: in std_logic;
shift: in std_logic;
CI: in std_logic;
S : out std_logic_vector(1 downto 0);
C0: out std_logic);
end adder2bitwithregjuga;

architecture arch of adder2bitwithregjuga is
-- Specify the Full Adder subcircuit
component Full_Adder
port
(AI,BI,CYI: in std_logic;
SUM, CYO :out std_logic);
end component;

--Reserve a few signals for internal connections
--signal CY0, CY1, CY2: bit;
signal flag: std_logic;
signal CY0: std_logic;
signal A,B : std_logic_vector(1 downto 0);
begin
FA0: Full_Adder port map (A(0), B(0), CI, S(0), CY0);
FA1: Full_Adder port map (A(1), B(1), CY0, S(1), C0);
process(clock)
begin
flag <= clock and shift;
if rising_edge(flag) then
A(1) <= A(0);
A(0) <= Ain;
B(1) <= B(0);
B(0) <= Bin;
end if;
end process;

end arch;

entity Full_Adder is
port
(AI,BI,CYI: in bit;
SUM, CYO : out bit);
end Full_Adder;

architecture FA of Full_Adder is
component Half_Adder
port
(W,X: in bit;
Y,Z: out bit);
end component;
signal Y0,Z0,Z1: bit;
begin
HA0: Half_Adder port map(AI, BI, Y0, Z0);
HA1: Half_Adder port map(CYI, Y0, SUM, Z1);
CYO <= Z0 or Z1;
end FA;

entity Half_Adder is
port
(W,X: in bit;
Y,Z: out bit);
end Half_Adder;

architecture HA of Half_Adder is
begin
Y <= W xor X; -- This is the sum bit
Z <= W and X; -- This is the carry bit
end HA;

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