More tristate buffer


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity tristate is
generic( width : integer := 7 );
port ( enA, enB, enC : in std_logic;
A, B: in std_logic_vector( width downto 0);
C : out std_logic_vector( width downto 0)
);
end tristate;

architecture rtl of tristate is
signal tribus : std_logic_vector ( width downto 0 );
begin
process(enA, enB, A, B)
begin
if enA = '1' then
tribus <= A;
elsif enB = '1' then
tribus <= B;
else
tribus <= "ZZZZZZZZ";
end if;

end process;

process(enC)
begin
if enC = '1' then
C <= tribus;
end if;
end process;
end rtl;

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