LUT and Tristate buffer


library ieee;
use ieee.std_logic_1164.all;

entity lutmulCGver2 is
port (
clk : in std_logic;
e : in std_logic;
r : in std_logic;
a, b: in std_logic_vector(3 downto 0);
c: out std_logic_vector(3 downto 0);
i, j, k : out std_logic_vector(3 downto 0);
enA, enB, enC : in std_logic
);
end entity lutmulCGver2;

architecture behavioral of lutmulCGver2 is
-- signal i : integer range 0 to 6:=0;
-- signal j : integer range 0 to 6:=0;
signal tribus : std_logic_vector ( 3 downto 0 );
signal enable : std_logic:='0';
type alog is array (0 to 2**3 - 2) of std_logic_vector(3 downto 0);
constant my_alog : alog := (
0 => "0001",
1 => "0010",
2 => "0100",
3 => "0011",
4 => "0110",
5 => "1111",
6 => "0101");

type log is array (1 to 2**3 - 1) of std_logic_vector(3 downto 0);
-- type log is array (1 to 2**3 - 1) of integer;
constant my_log : log := (
1 => "0000",
2 => "0001",
3 => "0011",
4 => "0010",
5 => "0110",
6 => "0100",
7 => "0101");

begin

process(enA, enB, a, b)
begin
if enA = '1' then
tribus <= a;
elsif enB = '1' then
tribus <= b;
else
tribus <= "ZZZZ";
end if;
end process;

process(enC)
begin
if enC = '1' then
c <= "0000";
end case;
end if;
-- k <= (i xor j) xor "1011"; -- xor untuk mereduksi, tapi hanya
berlaku untuk kalau generatornya x atau x+1
end process;
end architecture behavioral;

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