3 bit 2-to-1 mux


--CG praktikum lagi
--Dec 29th 2010
--3 bit 2-to-1 mux

library ieee;
use ieee.std_logic_1164.all;

entity LabExCG5 is
port
( a0, a1, a2, b0, b1, b2 : in bit;
sel : in bit;
m_out0, m_out1, m_out2 : out bit);
end LabExCG5;

architecture Behavior of LabExCG5 is
component MUX_2_TO_1
port
(x,y: in bit;
s: in bit;
m: out bit);
end component;
begin
MUX0: MUX_2_TO_1 port map (a0, b0, sel, m_out0);
MUX1: MUX_2_TO_1 port map (a1, b1, sel, m_out1);
MUX2: MUX_2_TO_1 port map (a2, b2, sel, m_out2);
end Behavior;

entity MUX_2_TO_1 is
port
(x,y: in bit;
s: in bit;
m: out bit);
end MUX_2_TO_1;

 

architecture M2TO1 of MUX_2_TO_1 is
begin
m <= (NOT(s) AND x) OR (s AND y);
end M2TO1;

revised version (watch the difference, especially the RTL):


library ieee;
use ieee.std_logic_1164.all;

entity LabExCG5 is
port
( a, b: in bit_vector(2 downto 0);
sel : in bit;
m_out : out bit_vector(2 downto 0));
end LabExCG5;

architecture Behavior of LabExCG5 is
component MUX_2_TO_1
port
(x,y: in bit;
s: in bit;
m: out bit);
end component;
begin
MUX0: MUX_2_TO_1 port map (a(0), b(0), sel, m_out(0));
MUX1: MUX_2_TO_1 port map (a(1), b(1), sel, m_out(1));
MUX2: MUX_2_TO_1 port map (a(2), b(2), sel, m_out(2));
end Behavior;

entity MUX_2_TO_1 is
port
(x,y: in bit;
s: in bit;
m: out bit);
end MUX_2_TO_1;

 

architecture M2TO1 of MUX_2_TO_1 is
begin
m <= (NOT(s) AND x) OR (s AND y);
end M2TO1;

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