3 bit 5-to-1 mux



--CG praktikum lagi
--Dec 30th 2010
--3 bit 5-to-1 mux

library ieee;
use ieee.std_logic_1164.all;

entity LabExCG6 is
port (--u, v, w, x, y : in std_logic_vector(2 downto 0);
-- s : in std_logic_vector(2 downto 0);
-- m : out std_logic_vector(2 downto 0)
u0, u1, u2 : in bit;
v0, v1, v2 : in bit;
w0, w1, w2 : in bit;
x0, x1, x2 : in bit;
y0, y1, y2 : in bit;
s0, s1, s2 : in bit;
m0, m1, m2 : out bit
);

end LabExCG6;

architecture Behavior of LabExCG6 is
component MUX_3_BIT_2_TO_1
port
(--x,y: in std_logic_vector(2 downto 0);
--s: in std_logic_vector(2 downto 0);
--m: out std_logic_vector(2 downto 0)
a0, a1, a2, b0, b1, b2 : in bit;
sel : in bit;
m_out0, m_out1, m_out2 : out bit
);
end component;
signal m00, m01, m02, m10, m11, m12, m20, m21, m22: bit;
begin
MUX0: MUX_3_BIT_2_TO_1 port map (u0, u1, u2, v0, v1, v2, s0, m00, m01, m02);
MUX1: MUX_3_BIT_2_TO_1 port map (w0, w1, w2, x0, x1, x2, s0, m10, m11, m12);
MUX2: MUX_3_BIT_2_TO_1 port map (m00, m01, m02, m10, m11, m12, s1, m20, m21, m22);
MUX3: MUX_3_BIT_2_TO_1 port map (m20, m21, m22, y0, y1, y2, s2, m0, m1, m2);
-- MUX0: MUX_3_BIT_2_TO_1 port map (u, v, s(0), m1);
-- MUX1: MUX_3_BIT 2_TO_1 port map (w, x, s(0), m2);
-- MUX2: MUX_3_BIT_2_TO_1 port map (m1, m2, s(1), m3);
-- MUX3: MUX_3_BIT_2_TO_1 port map (m3, y, s(2), m);
end Behavior;

--entity LabExCG6 is
entity MUX_3_BIT_2_TO_1 is
port
( --a, b: in std_logic_vector(2 downto 0);
a0, a1, a2, b0, b1, b2 : in bit;
sel : in bit;
-- m_out : out std_logic_vector(2 downto 1));
m_out0, m_out1, m_out2 : out bit);
end MUX_3_BIT_2_TO_1;
--end LabExCG6;

architecture M3BIT2TO1 of MUX_3_BIT_2_TO_1 is
--architecture Behavior of LabExCG6 is
component MUX_2_TO_1
port
(x,y: in bit;
s: in bit;
m: out bit);
end component;
begin
MUX0: MUX_2_TO_1 port map (a0, b0, sel, m_out0);
MUX1: MUX_2_TO_1 port map (a1, b1, sel, m_out1);
MUX2: MUX_2_TO_1 port map (a2, b2, sel, m_out2);
-- MUX0: MUX_2_TO_1 port map (a(0), b(0), sel, m_out(0));
-- MUX1: MUX_2_TO_1 port map (a(1), b(1), sel, m_out(1));
-- MUX2: MUX_2_TO_1 port map (a(2), b(2), sel, m_out(2));
end M3BIT2TO1;
--end Behavior;

entity MUX_2_TO_1 is
port
(x,y: in bit;
s: in bit;
m: out bit);
end MUX_2_TO_1;

architecture M2TO1 of MUX_2_TO_1 is
begin
m <= (NOT(s) AND x) OR (s AND y);
end M2TO1;

 

this is the revised code. much simpler

library ieee;
use ieee.std_logic_1164.all;

entity LabExCG6 is
port (u, v, w, x, y : in bit_vector(2 downto 0);
s : in bit_vector(2 downto 0);
m : out bit_vector(2 downto 0)
);
end LabExCG6;

architecture Behavior of LabExCG6 is
component MUX_3_BIT_2_TO_1
port
(a,b: in bit_vector(2 downto 0);
sel: in bit;
m_out: out bit_vector(2 downto 0)
);
end component;
signal m0, m1, m2: bit_vector(2 downto 0);
begin
MUX0: MUX_3_BIT_2_TO_1 port map (u, v, s(0), m0);
MUX1: MUX_3_BIT_2_TO_1 port map (w, x, s(0), m1);
MUX2: MUX_3_BIT_2_TO_1 port map (m0, m1, s(1), m2);
MUX3: MUX_3_BIT_2_TO_1 port map (m2, y, s(2), m);
end Behavior;

entity MUX_3_BIT_2_TO_1 is
port
( a, b: in bit_vector(2 downto 0);
sel : in bit;
m_out : out bit_vector(2 downto 0));
end MUX_3_BIT_2_TO_1;

architecture M3BIT2TO1 of MUX_3_BIT_2_TO_1 is
component MUX_2_TO_1
port
(x,y: in bit;
s: in bit;
m: out bit);
end component;
begin
MUX0: MUX_2_TO_1 port map (a(0), b(0), sel, m_out(0));
MUX1: MUX_2_TO_1 port map (a(1), b(1), sel, m_out(1));
MUX2: MUX_2_TO_1 port map (a(2), b(2), sel, m_out(2));
end M3BIT2TO1;

entity MUX_2_TO_1 is
port
(x,y: in bit;
s: in bit;
m: out bit);
end MUX_2_TO_1;

architecture M2TO1 of MUX_2_TO_1 is
begin
m <= (NOT(s) AND x) OR (s AND y);
end M2TO1;

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