## Testing non-composite & composite operation with Python

for 299 bit.

Thx for Fajar Yuliawan for the code. I’m going to use this for testing the multiplier design.

2. Phyton tutorial is here.

• #### ismailsunni 10:04 pm on July 3, 2011 Permalink | Reply

the only thing that I understand from this post –> Fajar Yuliawan…

🙂

## PERL – A Start

ok. have to learn perl too. it’s too cool so i have to learn 🙂

## Simple FSM

—————————————————–
— FSM for multiplier
— CG – 21 Jan 2011
—————————————————–

library ieee ;
use ieee.std_logic_1164.all;

—————————————————–

entity fsm_multiplierCG_1 is
port(
A0,A1,A2,A3: in bit_vector(1 downto 0);
opA : out bit_vector(1 downto 0);
clock: in std_logic;
reset: in std_logic
);
end fsm_multiplierCG_1;

—————————————————–

architecture FSM of fsm_multiplierCG_1 is

— define the states of FSM model

type state_type is (S0, S1, S2, S3);
signal next_state, current_state: state_type;

begin

— cocurrent process#1: state registers
state_reg: process(clock, reset)
begin

if (reset=’1′) then
current_state <= S0;
elsif (clock’event and clock=’1′) then
current_state <= next_state;
end if;

end process;

— cocurrent process#2: combinational logic
comb_logic: process(current_state, clock)
begin

— use case statement to show the
— state transistion

case current_state is

when S0 => opA <= A0;
next_state <= S1;

when S1 => opA <= A1;
next_state <= S2;

when S2 => opA <= A2;
next_state <= S3;

when S3 => opA <= A3;
next_state <= S0;

end case;

end process;

end FSM;

—————————————————–

## R Programming – A Start

Now phd student has to learn R 🙂

## Polynomial reducer

ok. my algorithm works.

## 299 classic multiplier

… took forever to compile, and does not fit.

the super long code generated using perl. with the help of master shifu, thank you 🙂

• #### Budi Rahardjo 9:41 pm on January 19, 2011 Permalink | Reply

Good job! Excellente … Now, code your approach (comp.)

## Xilinx vs Altera

I have problems comparing gate number for FPGA implementation using Xilinx with implementation using Altera. They use different building blocks. Xilinx uses terms like slices LUT (Look Up Table),FF (Flip Flop) and LC (Logic Cell) while Altera uses LE (Logic Elements).

Here said that the logic cell to logic element ratio is 1.125:1, despite generally similar functionality. Therefore, divide Xilinx’s stated LC count by 1.125 to get the equivalent Altera LE count. More details here.

This link compares Xilinx and Altera FPGA logic comparison. And this is a guide on how to choose between those two.

This site mentions that:
Xilinx: 1 slices = 2 LUT + 2 FF + some more logic
Altera: 1 LE = 1 LUT + 1FF + some more logic
So 1 slice (xilinx) = 2 LE (altera).

## Back to paper and pencil

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