Updates from February, 2011 Toggle Comment Threads | Keyboard Shortcuts

  • CG 3:15 pm on February 25, 2011 Permalink | Reply
    Tags: finite field, look up table, , , ,   

    4 bits LUT-based multiplier 

    LUT_BR. vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity LUT_BR is
    port (
    clk : in std_logic;
    a, b: in std_logic_vector(3 downto 0);
    c: out std_logic_vector(3 downto 0);
    porti : out std_logic_vector(3 downto 0);
    portj : out std_logic_vector(3 downto 0);
    portk : out std_logic_vector(3 downto 0)
    );
    end entity LUT_BR;

    architecture behavioral of LUT_BR is
    component adder_mod_m_CG
    port (
    x, y: in std_logic_vector(3 downto 0);
    addb_sub: in std_logic;
    z: buffer std_logic_vector(3 downto 0)
    );
    end component;

    signal z : std_logic := ‘0’;
    signal i : std_logic_vector(3 downto 0);
    signal j : std_logic_vector(3 downto 0);
    signal k : std_logic_vector(3 downto 0);

    begin

    process (clk)
    begin
    if clk’event and clk = ‘1’ then
    case a is
    when "0001" => i <= "0000";
    when "0010" => i <= "0001";
    when "0011" => i <= "0011";
    when "0100" => i <= "0010";
    when "0101" => i <= "0110";
    when "0110" => i <= "0100";
    when "0111" => i <= "0101";
    when others => i <= "0000";
    end case;
    case b is
    when "0001" => j <= "0000";
    when "0010" => j <= "0001";
    when "0011" => j <= "0011";
    when "0100" => j <= "0010";
    when "0101" => j <= "0110";
    when "0110" => j <= "0100";
    when "0111" => j <= "0101";
    when others => j <= "0000";
    end case;
    case k is
    when "0000" => c <= "0001";
    when "0001" => c <= "0010";
    when "0010" => c <= "0100";
    when "0011" => c <= "0011";
    when "0100" => c <= "0110";
    when "0101" => c <= "0111";
    when "0110" => c <= "0101";
    when others => c <= "0000";
    end case;
    end if;

    end process;

    adderku: adder_mod_m_CG port map (i, j, z, k);
    porti <= i;
    portj <= j;
    portk <= k;

    end architecture behavioral;

    adder_mod_m_CG.vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

    entity adder_mod_m_CG is
    port (
    x, y: in std_logic_vector(3 downto 0);
    addb_sub: in std_logic;
    z: out std_logic_vector(3 downto 0)
    );
    end adder_mod_m_CG;

    architecture rtl of adder_mod_m_CG is
    constant M: std_logic_vector(3 downto 0) := conv_std_logic_vector(7, 4);
    signal long_x, xor_y, sum1, long_z1, xor_m, sum2: std_logic_vector(4 downto 0);
    signal c1, c2, sel: std_logic;
    signal z1, z2: std_logic_vector(3 downto 0);

    begin

    long_x <= ‘0’ & x;
    xor_gates1: for i in 0 to 3 generate
    xor_y(i) <= y(i) xor addb_sub;
    end generate;
    xor_y(4) <= ‘0’;
    sum1 <= addb_sub + long_x + xor_y;
    c1 <= sum1(4);
    z1 <= sum1(3 downto 0);
    long_z1 <= ‘0’ & z1;
    xor_gates2: for i in 0 to 3 generate
    xor_m(i) <= m(i) xor not(addb_sub);
    end generate;
    xor_m(4) <= ‘0’;
    sum2 <= not(addb_sub) + long_z1 + xor_m;
    c2 <= sum2(4);
    z2 <= sum2(3 downto 0);
    sel <= (not(addb_sub) and (c1 or c2)) or (addb_sub and not(c1));
    with sel select z <= z1 when ‘0’, z2 when others;

    end rtl;

    Pair programming always works 🙂 Thank you Guru 🙂

     
  • CG 2:43 pm on February 19, 2011 Permalink | Reply
    Tags: , signal, variable,   

    Signal vs variable in VHDL 

    Signals are similar to hardware and are not updated until the end of a process. Variables are immediately updated. Xilinx recommends using signals for hardware descriptions; however, variables allow quick simulation.

    If several values are assigned to a signal in one process, only the final value is used. When a value is assigned to a variable, the assignment takes place immediately. A variable maintains its value until a new value specified.

    Signal:
    Library IEEE;
    use IEEE.std_logic_1164.all;
    entity xor_sig is

    port (A, B, C: in STD_LOGIC;
    X, Y: out STD_LOGIC);
    end xor_sig;

    architecture SIG_ARCH of xor_sig is
    signal D: STD_LOGIC;
    begin
    SIG:process (A,B,C)
    begin
    D <= A; — ignored !!
    X <= C xor D;
    D <= B; — overrides !!
    Y <= C xor D;
    end process;
    end SIG_ARCH;

    Variable:
    Library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all;

    entity xor_var is
    port (A, B, C: in STD_LOGIC;
    X, Y: out STD_LOGIC);
    end xor_var;

    architecture VAR_ARCH of xor_var is
    begin

    VAR:process (A,B,C)
    variable D: STD_LOGIC;
    begin
    D := A;
    X <= C xor D;
    D := B;
    Y <= C xor D;
    end process;
    end VAR_ARCH;

    Useful links:

    1. http://www.xilinx.com/itp/xilinx4/data/docs/sim/coding4.html
    2. http://www.gmvhdl.com/signals.htm
     
    • Budi Rahardjo 3:58 pm on February 19, 2011 Permalink | Reply

      bagus untuk memahami semantics dari keduanya

      • CG 5:39 pm on February 19, 2011 Permalink | Reply

        liat deh hasilnya. kalau pake signal D -nya gak berubah walau di initiate ke A

  • CG 4:09 pm on February 3, 2011 Permalink | Reply
    Tags: cron, crontab   

    Using Cron 

    Format:
    [Minute (0-59)] [Hour (0-23)] [Day (1-31)] [Month (1-12)] [Weekday (0-6, where 0 indicates Sunday)] /some/script/or/command

    Notes:
    crontab -e for editing
    crontab -l for listing all crons have been configured in the machine
    crontab -r for removing crontab files for the user

    Useful links:

    1. http://www.crontabrocks.org/
    2. http://www.thegeekstuff.com/2009/06/15-practical-crontab-examples/
    3. http://adminschoice.com/crontab-quick-reference
    4. http://www.linuxhelp.net/guides/cron/
    5. http://en.wikipedia.org/wiki/Cron
     
c
Compose new post
j
Next post/Next comment
k
Previous post/Previous comment
r
Reply
e
Edit
o
Show/Hide comments
t
Go to top
l
Go to login
h
Show/Hide help
shift + esc
Cancel