Signal vs variable in VHDL

Signals are similar to hardware and are not updated until the end of a process. Variables are immediately updated. Xilinx recommends using signals for hardware descriptions; however, variables allow quick simulation.

If several values are assigned to a signal in one process, only the final value is used. When a value is assigned to a variable, the assignment takes place immediately. A variable maintains its value until a new value specified.

Signal:
Library IEEE;
use IEEE.std_logic_1164.all;
entity xor_sig is

port (A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC);
end xor_sig;

architecture SIG_ARCH of xor_sig is
signal D: STD_LOGIC;
begin
SIG:process (A,B,C)
begin
D <= A; — ignored !!
X <= C xor D;
D <= B; — overrides !!
Y <= C xor D;
end process;
end SIG_ARCH;

Variable:
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity xor_var is
port (A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC);
end xor_var;

architecture VAR_ARCH of xor_var is
begin

VAR:process (A,B,C)
variable D: STD_LOGIC;
begin
D := A;
X <= C xor D;
D := B;
Y <= C xor D;
end process;
end VAR_ARCH;

Useful links:

  1. http://www.xilinx.com/itp/xilinx4/data/docs/sim/coding4.html
  2. http://www.gmvhdl.com/signals.htm
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