Generic map error in VHDL

Still can’t make this work.


library ieee;
use ieee. std_logic_1164.all;

entity generic_demo is
port(
clk, reset: in std_logic;
q_4: out std_logic_vector(3 downto 0);
q_12: out std_logic_vector(11 downto 0)
);
end generic_demo;

architecture vhdl_87_arch of generic_demo is
component para_binary_counter
generic (WIDTH: natural);
port(
clk, reset: in std_logic;
q: out std_logic_vector(WIDTH-1 downto 0)
);
end component;

begin
four_bit: para_binary_counter
generic map (WIDTH=>4)
port map(clk=>clk, reset=>reset, q=>q_4);
twe_bit: para_binary_counter
generic map (WIDTH=>12)
port map(clk=>clk, reset=>reset, q=>q_12);
end vhdl_87_arch;

Error message:

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