Generic map in vhdl now works

Yay! I’ve got useful advices from the previous posting, and now it works 🙂 Thanks 🙂

All I need to do is adding this code in separated file, and then compile.

library ieee;
use ieee. std_logic_1164.all;

entity para_binary_counter is
generic (WIDTH: natural);
port(
clk, reset: in std_logic;
q: out std_logic_vector(WIDTH-1 downto 0)
);
end para_binary_counter;

architecture arch of para_binary_counter is
begin
end arch;

Now it works 🙂

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