## Polynomial Basis Squaring

Finally have successfully found some spare time to do coding to solve this polynomial squaring:

And this is the result, x^5 + x + 1 :

• #### rudi 9:37 pm on May 30, 2013 Permalink | Reply

bu, akan lebih cantik kalo nulis polinomnya pake latex,
$x^5 + x+1$

• #### CG 11:00 am on May 31, 2013 Permalink | Reply

iya belum sempet dirapihin 😀 biasanya saya pake latex for wordpress

• #### Akshay 11:18 pm on July 26, 2013 Permalink | Reply

Hey please mail me this complete C code. sorry I’m not execute this ….please help me…please ..

## Drawing Elliptic Curve with Geometer Sketchpad

Point Doubling:

Associative:

[*Note: Big thanks for Fajar Yuliawan for his brilliant tutorial 😉 ]

• #### Budi Rahardjo 2:39 pm on November 4, 2011 Permalink | Reply

yay! good stuff …

• #### CG 3:15 pm on April 6, 2011 Permalink | Reply Tags: composite field ( 16 )

http://www.math.kau.se/igorgach/Statji/statja(2010)1.pdf

## 4 bits LUT-based multiplier

LUT_BR. vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity LUT_BR is
port (
clk : in std_logic;
a, b: in std_logic_vector(3 downto 0);
c: out std_logic_vector(3 downto 0);
porti : out std_logic_vector(3 downto 0);
portj : out std_logic_vector(3 downto 0);
portk : out std_logic_vector(3 downto 0)
);
end entity LUT_BR;

architecture behavioral of LUT_BR is
port (
x, y: in std_logic_vector(3 downto 0);
z: buffer std_logic_vector(3 downto 0)
);
end component;

signal z : std_logic := ‘0’;
signal i : std_logic_vector(3 downto 0);
signal j : std_logic_vector(3 downto 0);
signal k : std_logic_vector(3 downto 0);

begin

process (clk)
begin
if clk’event and clk = ‘1’ then
case a is
when "0001" => i <= "0000";
when "0010" => i <= "0001";
when "0011" => i <= "0011";
when "0100" => i <= "0010";
when "0101" => i <= "0110";
when "0110" => i <= "0100";
when "0111" => i <= "0101";
when others => i <= "0000";
end case;
case b is
when "0001" => j <= "0000";
when "0010" => j <= "0001";
when "0011" => j <= "0011";
when "0100" => j <= "0010";
when "0101" => j <= "0110";
when "0110" => j <= "0100";
when "0111" => j <= "0101";
when others => j <= "0000";
end case;
case k is
when "0000" => c <= "0001";
when "0001" => c <= "0010";
when "0010" => c <= "0100";
when "0011" => c <= "0011";
when "0100" => c <= "0110";
when "0101" => c <= "0111";
when "0110" => c <= "0101";
when others => c <= "0000";
end case;
end if;

end process;

adderku: adder_mod_m_CG port map (i, j, z, k);
porti <= i;
portj <= j;
portk <= k;

end architecture behavioral;

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

port (
x, y: in std_logic_vector(3 downto 0);
z: out std_logic_vector(3 downto 0)
);

architecture rtl of adder_mod_m_CG is
constant M: std_logic_vector(3 downto 0) := conv_std_logic_vector(7, 4);
signal long_x, xor_y, sum1, long_z1, xor_m, sum2: std_logic_vector(4 downto 0);
signal c1, c2, sel: std_logic;
signal z1, z2: std_logic_vector(3 downto 0);

begin

long_x <= ‘0’ & x;
xor_gates1: for i in 0 to 3 generate
xor_y(i) <= y(i) xor addb_sub;
end generate;
xor_y(4) <= ‘0’;
sum1 <= addb_sub + long_x + xor_y;
c1 <= sum1(4);
z1 <= sum1(3 downto 0);
long_z1 <= ‘0’ & z1;
xor_gates2: for i in 0 to 3 generate
xor_m(i) <= m(i) xor not(addb_sub);
end generate;
xor_m(4) <= ‘0’;
sum2 <= not(addb_sub) + long_z1 + xor_m;
c2 <= sum2(4);
z2 <= sum2(3 downto 0);
sel <= (not(addb_sub) and (c1 or c2)) or (addb_sub and not(c1));
with sel select z <= z1 when ‘0’, z2 when others;

end rtl;

Pair programming always works 🙂 Thank you Guru 🙂

## Testing non-composite & composite operation with Python

for 299 bit.

Thx for Fajar Yuliawan for the code. I’m going to use this for testing the multiplier design.

1. Phyton for mac can be downloaded here.
2. Phyton tutorial is here.

• #### ismailsunni 10:04 pm on July 3, 2011 Permalink | Reply

the only thing that I understand from this post –> Fajar Yuliawan…

🙂

## Simple FSM

—————————————————–
— FSM for multiplier
— CG – 21 Jan 2011
—————————————————–

library ieee ;
use ieee.std_logic_1164.all;

—————————————————–

entity fsm_multiplierCG_1 is
port(
A0,A1,A2,A3: in bit_vector(1 downto 0);
opA : out bit_vector(1 downto 0);
clock: in std_logic;
reset: in std_logic
);
end fsm_multiplierCG_1;

—————————————————–

architecture FSM of fsm_multiplierCG_1 is

— define the states of FSM model

type state_type is (S0, S1, S2, S3);
signal next_state, current_state: state_type;

begin

— cocurrent process#1: state registers
state_reg: process(clock, reset)
begin

if (reset=’1′) then
current_state <= S0;
elsif (clock’event and clock=’1′) then
current_state <= next_state;
end if;

end process;

— cocurrent process#2: combinational logic
comb_logic: process(current_state, clock)
begin

— use case statement to show the
— state transistion

case current_state is

when S0 => opA <= A0;
next_state <= S1;

when S1 => opA <= A1;
next_state <= S2;

when S2 => opA <= A2;
next_state <= S3;

when S3 => opA <= A3;
next_state <= S0;

end case;

end process;

end FSM;

—————————————————–

## Polynomial reducer

ok. my algorithm works.

• #### CG 3:11 pm on December 17, 2010 Permalink | Reply Tags: ECC ( 14 ), elliptic curve cryptography ( 3 ), plaintext embedding ( 5 )

Mapping an Arbitrary Message to an Elliptic Curve when Defined over GF(2^n), Brian King, Indiana University – Purdue University Indianapolis 723 W Michigan, SL 160 Indianapolis, IN 46202International Journal of Network Security, Vol.8, No.2, PP.169–176, Mar. 2009.

• #### Johnb282 9:24 pm on May 28, 2014 Permalink | Reply

certainly like your website however you have to check the spelling on several of your posts. Many of them are rife with spelling problems and I to find it very troublesome to inform the truth nevertheless I will surely come back again. eafkedkbdegg

## Key Lengths – Arjen K. Lenstra

Key Lengths – Contribution to The Handbook of Information Security, Arjen K. Lenstra Lucent Technologies and TechnischeUniversiteit Eindhoven 1 North Gate Road, Mendham, NJ 07945-3104, U.S.A., June 30, 2004

## PB preference over ONB

In principle there are no restrictions on the kind of basis that is used (polynomial, normal, …). Although more work has to be done on this, we believe that a polynomial basis is most suited because a number of the advantages of (optimal) normal basis disappear when r > 1.

[Erik De Win, Antoon Bosselaers, Servaas Vandenberghe, Peter De Gersem, Joos Vandewalle, “A Fast Software Implementation for Arithmetic Operations in GF(2^n)“, Katholieke Universiteit Leuven, Belgium]

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