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  • CG 2:30 pm on October 21, 2010 Permalink | Reply
    Tags: adder, , , , register,   

    Adder with register 


    library ieee;
    use ieee.std_logic_1164.all;

    entity adder2bitwithregjuga is
    port
    (clock: in std_logic;
    Ain: in std_logic;
    Bin: in std_logic;
    shift: in std_logic;
    CI: in std_logic;
    S : out std_logic_vector(1 downto 0);
    C0: out std_logic);
    end adder2bitwithregjuga;

    architecture arch of adder2bitwithregjuga is
    -- Specify the Full Adder subcircuit
    component Full_Adder
    port
    (AI,BI,CYI: in std_logic;
    SUM, CYO :out std_logic);
    end component;

    --Reserve a few signals for internal connections
    --signal CY0, CY1, CY2: bit;
    signal flag: std_logic;
    signal CY0: std_logic;
    signal A,B : std_logic_vector(1 downto 0);
    begin
    FA0: Full_Adder port map (A(0), B(0), CI, S(0), CY0);
    FA1: Full_Adder port map (A(1), B(1), CY0, S(1), C0);
    process(clock)
    begin
    flag <= clock and shift;
    if rising_edge(flag) then
    A(1) <= A(0);
    A(0) <= Ain;
    B(1) <= B(0);
    B(0) <= Bin;
    end if;
    end process;

    end arch;

    entity Full_Adder is
    port
    (AI,BI,CYI: in bit;
    SUM, CYO : out bit);
    end Full_Adder;

    architecture FA of Full_Adder is
    component Half_Adder
    port
    (W,X: in bit;
    Y,Z: out bit);
    end component;
    signal Y0,Z0,Z1: bit;
    begin
    HA0: Half_Adder port map(AI, BI, Y0, Z0);
    HA1: Half_Adder port map(CYI, Y0, SUM, Z1);
    CYO <= Z0 or Z1;
    end FA;

    entity Half_Adder is
    port
    (W,X: in bit;
    Y,Z: out bit);
    end Half_Adder;

    architecture HA of Half_Adder is
    begin
    Y <= W xor X; -- This is the sum bit
    Z <= W and X; -- This is the carry bit
    end HA;

     
    • Bobby 4:46 pm on October 21, 2010 Permalink | Reply

      HORRROOOORRR

    • Budi Rahardjo 2:03 pm on October 23, 2010 Permalink | Reply

      liat tuh di kodenya sampe ada yang ketawa (smiley)… he he he

      • CG 6:38 pm on October 23, 2010 Permalink | Reply

        itu bukan smile tapi lagi teriak “HORRROOOORRR! ” hihihihihi

  • CG 12:09 pm on October 13, 2010 Permalink | Reply
    Tags: adder, , , waveform   

    13bit adder 

    Don’t laugh. I’m still doing this and I want to make sure this is documented and can be easily use later for reference.


    library ieee;
    use ieee.std_logic_1164.all;

    entity adder13bit is
    port (clock, Ain, Bin : in std_logic;
    Aout, Bout, Cout : out std_logic;
    shift_in: in std_logic);
    end entity adder13bit;

    architecture rtl of adder13bit is
    signal flag: std_logic;
    signal a, b, c: std_logic_vector(12 downto 0);
    begin
    process(clock)
    begin
    flag <= clock and shift_in;
    if rising_edge(flag) then
    Aout <= a(12);
    Bout <= b(12);
    for N in 12 downto 1 loop
    a(N) <= A(N-1);
    b(N) <= B(N-1);
    end loop;
    a(0) <= Ain;
    b(0) <= Bin;
    end if;

    for N in 12 downto 0 loop
    c(N) <= A(N) xor B(N);
    Cout <= c(N);
    end loop;
    end process;
    end architecture rtl;

     
    • Budi Rahardjo 4:41 am on October 14, 2010 Permalink | Reply

      Good. Tapi formating program VHDL nya kok kacau. WordPress gak support VHDL?

      • CG 2:48 pm on October 14, 2010 Permalink | Reply

        iya gak support. kalau lyx sih support VHDL, yay 🙂

  • CG 10:04 pm on October 1, 2010 Permalink | Reply
    Tags: adder, , , xor   

    It never fits [not talking about clothes] 

    120 is the closest. while what we need is 299.

     
    • CG 10:32 pm on October 1, 2010 Permalink | Reply

      kecurigaan sementara: penggunaan port/pin. dipikirin besok lagi. now time to zzz.

      • asp 12:56 pm on October 2, 2010 Permalink | Reply

        chipnya nanti kan inputnya hanya text yang dienkrip sama key bukan?
        kayaknya perlu dijadiin dulu semua baru mikirin efisiensi pin/port.

    • CG 5:28 am on October 2, 2010 Permalink | Reply

      Warning: found 121 output pins without output pin load capacitance assignment.

    • CG 5:29 am on October 2, 2010 Permalink | Reply

      Warning: The Reserve All Unused Pins setting has not been specified, and will default to ‘As output driving ground’.

    • CG 5:49 am on October 2, 2010 Permalink | Reply

    • Budi Rahardjo 6:25 am on October 4, 2010 Permalink | Reply

      Kalau warning itu hanya karena konfigurasi dari Quartus saja. Bisa diignore sekarang, tetapi yang menjadi masalah adalah kenapa hanya bisa 120 komponen saja dan kenapa output setiap komponen diasosiasikan dengan satu pin. Itu yang jadi masalah kayaknya. Time to read VHDL again.

      • CG 10:00 am on October 4, 2010 Permalink | Reply

        yes i’m reading vhdl manuals again. i’m thinking to continue the multiplication in the ground field but still i haven’t figured out how to deal with lut reading and writing 😦

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