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  • CG 10:18 pm on June 1, 2012 Permalink | Reply
    Tags: fpga, gates, Logic Elements, Stratix II,   

    LE to gates 

    anybody knows stratix ii device LE (Logic Elements) equivalence in gates?

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  • CG 3:14 pm on April 19, 2011 Permalink | Reply
    Tags: , cyclone, fpga,   

    Logic Elements in Cyclone II 

    Some good references:

    1. http://idle-logic.com/2010/02/11/dissecting-the-cyclone-2-handbook-part1/
    2. http://www.cs.columbia.edu/~sedwards/classes/2011/4840/cyc2_cii5v1.pdf
    3. http://www.altera.com/literature/hb/cyc2/cyc2_cii5v1.pdf
    4. http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf
    5. http://www.altera.com/products/devices/cyclone2/features/cy2-features.html
    Note:
    Stratix Family is high-end FPGA while Cyclone Family is low-end FPGA (the mid-range FPGA is Arria).
     
  • CG 6:11 pm on January 12, 2011 Permalink | Reply
    Tags: , fpga, , xilinx   

    Xilinx vs Altera 

    I have problems comparing gate number for FPGA implementation using Xilinx with implementation using Altera. They use different building blocks. Xilinx uses terms like slices LUT (Look Up Table),FF (Flip Flop) and LC (Logic Cell) while Altera uses LE (Logic Elements).

    Here said that the logic cell to logic element ratio is 1.125:1, despite generally similar functionality. Therefore, divide Xilinx’s stated LC count by 1.125 to get the equivalent Altera LE count. More details here.

    This link compares Xilinx and Altera FPGA logic comparison. And this is a guide on how to choose between those two.

    This site mentions that:
    Xilinx: 1 slices = 2 LUT + 2 FF + some more logic
    Altera: 1 LE = 1 LUT + 1FF + some more logic
    So 1 slice (xilinx) = 2 LE (altera).

     
  • CG 6:39 pm on December 30, 2010 Permalink | Reply
    Tags: , fpga, , ,   

    3 bit 5-to-1 mux 



    --CG praktikum lagi
    --Dec 30th 2010
    --3 bit 5-to-1 mux

    library ieee;
    use ieee.std_logic_1164.all;

    entity LabExCG6 is
    port (--u, v, w, x, y : in std_logic_vector(2 downto 0);
    -- s : in std_logic_vector(2 downto 0);
    -- m : out std_logic_vector(2 downto 0)
    u0, u1, u2 : in bit;
    v0, v1, v2 : in bit;
    w0, w1, w2 : in bit;
    x0, x1, x2 : in bit;
    y0, y1, y2 : in bit;
    s0, s1, s2 : in bit;
    m0, m1, m2 : out bit
    );

    end LabExCG6;

    architecture Behavior of LabExCG6 is
    component MUX_3_BIT_2_TO_1
    port
    (--x,y: in std_logic_vector(2 downto 0);
    --s: in std_logic_vector(2 downto 0);
    --m: out std_logic_vector(2 downto 0)
    a0, a1, a2, b0, b1, b2 : in bit;
    sel : in bit;
    m_out0, m_out1, m_out2 : out bit
    );
    end component;
    signal m00, m01, m02, m10, m11, m12, m20, m21, m22: bit;
    begin
    MUX0: MUX_3_BIT_2_TO_1 port map (u0, u1, u2, v0, v1, v2, s0, m00, m01, m02);
    MUX1: MUX_3_BIT_2_TO_1 port map (w0, w1, w2, x0, x1, x2, s0, m10, m11, m12);
    MUX2: MUX_3_BIT_2_TO_1 port map (m00, m01, m02, m10, m11, m12, s1, m20, m21, m22);
    MUX3: MUX_3_BIT_2_TO_1 port map (m20, m21, m22, y0, y1, y2, s2, m0, m1, m2);
    -- MUX0: MUX_3_BIT_2_TO_1 port map (u, v, s(0), m1);
    -- MUX1: MUX_3_BIT 2_TO_1 port map (w, x, s(0), m2);
    -- MUX2: MUX_3_BIT_2_TO_1 port map (m1, m2, s(1), m3);
    -- MUX3: MUX_3_BIT_2_TO_1 port map (m3, y, s(2), m);
    end Behavior;

    --entity LabExCG6 is
    entity MUX_3_BIT_2_TO_1 is
    port
    ( --a, b: in std_logic_vector(2 downto 0);
    a0, a1, a2, b0, b1, b2 : in bit;
    sel : in bit;
    -- m_out : out std_logic_vector(2 downto 1));
    m_out0, m_out1, m_out2 : out bit);
    end MUX_3_BIT_2_TO_1;
    --end LabExCG6;

    architecture M3BIT2TO1 of MUX_3_BIT_2_TO_1 is
    --architecture Behavior of LabExCG6 is
    component MUX_2_TO_1
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end component;
    begin
    MUX0: MUX_2_TO_1 port map (a0, b0, sel, m_out0);
    MUX1: MUX_2_TO_1 port map (a1, b1, sel, m_out1);
    MUX2: MUX_2_TO_1 port map (a2, b2, sel, m_out2);
    -- MUX0: MUX_2_TO_1 port map (a(0), b(0), sel, m_out(0));
    -- MUX1: MUX_2_TO_1 port map (a(1), b(1), sel, m_out(1));
    -- MUX2: MUX_2_TO_1 port map (a(2), b(2), sel, m_out(2));
    end M3BIT2TO1;
    --end Behavior;

    entity MUX_2_TO_1 is
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end MUX_2_TO_1;

    architecture M2TO1 of MUX_2_TO_1 is
    begin
    m <= (NOT(s) AND x) OR (s AND y);
    end M2TO1;

     

    this is the revised code. much simpler

    library ieee;
    use ieee.std_logic_1164.all;

    entity LabExCG6 is
    port (u, v, w, x, y : in bit_vector(2 downto 0);
    s : in bit_vector(2 downto 0);
    m : out bit_vector(2 downto 0)
    );
    end LabExCG6;

    architecture Behavior of LabExCG6 is
    component MUX_3_BIT_2_TO_1
    port
    (a,b: in bit_vector(2 downto 0);
    sel: in bit;
    m_out: out bit_vector(2 downto 0)
    );
    end component;
    signal m0, m1, m2: bit_vector(2 downto 0);
    begin
    MUX0: MUX_3_BIT_2_TO_1 port map (u, v, s(0), m0);
    MUX1: MUX_3_BIT_2_TO_1 port map (w, x, s(0), m1);
    MUX2: MUX_3_BIT_2_TO_1 port map (m0, m1, s(1), m2);
    MUX3: MUX_3_BIT_2_TO_1 port map (m2, y, s(2), m);
    end Behavior;

    entity MUX_3_BIT_2_TO_1 is
    port
    ( a, b: in bit_vector(2 downto 0);
    sel : in bit;
    m_out : out bit_vector(2 downto 0));
    end MUX_3_BIT_2_TO_1;

    architecture M3BIT2TO1 of MUX_3_BIT_2_TO_1 is
    component MUX_2_TO_1
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end component;
    begin
    MUX0: MUX_2_TO_1 port map (a(0), b(0), sel, m_out(0));
    MUX1: MUX_2_TO_1 port map (a(1), b(1), sel, m_out(1));
    MUX2: MUX_2_TO_1 port map (a(2), b(2), sel, m_out(2));
    end M3BIT2TO1;

    entity MUX_2_TO_1 is
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end MUX_2_TO_1;

    architecture M2TO1 of MUX_2_TO_1 is
    begin
    m <= (NOT(s) AND x) OR (s AND y);
    end M2TO1;

     
    • CG 6:44 pm on December 30, 2010 Permalink | Reply

      still cannot understand why this doesnt work using std_logic_vector?

      • CG 9:16 pm on December 30, 2010 Permalink | Reply

        you should use bit_vector instead of std_logic_vector

  • CG 4:53 pm on December 30, 2010 Permalink | Reply
    Tags: , fpga, , ,   

    3 bit 2-to-1 mux 


    --CG praktikum lagi
    --Dec 29th 2010
    --3 bit 2-to-1 mux

    library ieee;
    use ieee.std_logic_1164.all;

    entity LabExCG5 is
    port
    ( a0, a1, a2, b0, b1, b2 : in bit;
    sel : in bit;
    m_out0, m_out1, m_out2 : out bit);
    end LabExCG5;

    architecture Behavior of LabExCG5 is
    component MUX_2_TO_1
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end component;
    begin
    MUX0: MUX_2_TO_1 port map (a0, b0, sel, m_out0);
    MUX1: MUX_2_TO_1 port map (a1, b1, sel, m_out1);
    MUX2: MUX_2_TO_1 port map (a2, b2, sel, m_out2);
    end Behavior;

    entity MUX_2_TO_1 is
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end MUX_2_TO_1;

     

    architecture M2TO1 of MUX_2_TO_1 is
    begin
    m <= (NOT(s) AND x) OR (s AND y);
    end M2TO1;

    revised version (watch the difference, especially the RTL):


    library ieee;
    use ieee.std_logic_1164.all;

    entity LabExCG5 is
    port
    ( a, b: in bit_vector(2 downto 0);
    sel : in bit;
    m_out : out bit_vector(2 downto 0));
    end LabExCG5;

    architecture Behavior of LabExCG5 is
    component MUX_2_TO_1
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end component;
    begin
    MUX0: MUX_2_TO_1 port map (a(0), b(0), sel, m_out(0));
    MUX1: MUX_2_TO_1 port map (a(1), b(1), sel, m_out(1));
    MUX2: MUX_2_TO_1 port map (a(2), b(2), sel, m_out(2));
    end Behavior;

    entity MUX_2_TO_1 is
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end MUX_2_TO_1;

     

    architecture M2TO1 of MUX_2_TO_1 is
    begin
    m <= (NOT(s) AND x) OR (s AND y);
    end M2TO1;

     
    • CG 5:06 pm on December 30, 2010 Permalink | Reply

      why this code doesnt work? because of the vectors?

      library ieee;
      use ieee.std_logic_1164.all;

      entity LabExCG5 is
      port
      ( a, b: in std_logic_vector(2 downto 0);
      sel : in bit;
      m_out : out std_logic_vector(2 downto 1));
      end LabExCG5;

      architecture Behavior of LabExCG5 is
      component MUX_2_TO_1
      port
      (x,y: in bit;
      s: in bit;
      m: out bit);
      end component;
      begin
      MUX0: MUX_2_TO_1 port map (a(0), b(0), sel, m_out(0));
      MUX1: MUX_2_TO_1 port map (a(1), b(1), sel, m_out(1));
      MUX2: MUX_2_TO_1 port map (a(2), b(2), sel, m_out(2));
      end Behavior;

      entity MUX_2_TO_1 is
      port
      (x,y: in bit;
      s: in bit;
      m: out bit);
      end MUX_2_TO_1;

      architecture M2TO1 of MUX_2_TO_1 is
      begin
      m <= (NOT(s) AND x) OR (s AND y);
      end M2TO1;

    • CG 5:07 pm on December 30, 2010 Permalink | Reply

      the error message is:
      Error (10381): VHDL Type Mismatch error at LabExCG5.vhd(52): indexed name returns a value whose type does not match “bit”, the type of the target expression

      • CG 10:33 pm on December 30, 2010 Permalink | Reply

        it solved by changing “std_logic_vector” into “bit_logic_vector”

  • CG 1:43 pm on December 6, 2010 Permalink | Reply
    Tags: 7 segment decoder, , fpga,   

    7-segment decoder 

    Lab Exercise:

    VHDL Code:

    --CG lagi praktikum
    -- 7-segment
    -- 5 Desember 2010

    Pin planner:

    *Important notes:
    Each segment is illuminated by driving it to the logic value 0

     
  • CG 3:45 pm on December 3, 2010 Permalink | Reply
    Tags: , fpga, , mux,   

    8-bit 2-to-1 multiplexer 

    Laboratory Exercise:

    RTL View:

    VHDL Code:

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;

    -- Simple module that connects the SW switches to the LEDR lights
    ENTITY LabExCG2 IS
    PORT( x0, x1, x2, x3, x4, x5, x6, x7 : IN BIT;
    y0, y1, y2, y3, y4, y5, y6, y7 : IN BIT;
    s : IN BIT;
    m0, m1, m2, m3, m4, m5, m6, m7 : OUT BIT);
    END LabExCG2;

    ARCHITECTURE Behavior OF LabExCG2 IS
    BEGIN
    m0 <= (NOT(s) AND x0) OR (s AND y0);
    m1 <= (NOT(s) AND x1) OR (s AND y1);
    m2 <= (NOT(s) AND x2) OR (s AND y2);
    m3 <= (NOT(s) AND x3) OR (s AND y3);
    m4 <= (NOT(s) AND x4) OR (s AND y4);
    m5 <= (NOT(s) AND x5) OR (s AND y5);
    m6 <= (NOT(s) AND x6) OR (s AND y6);
    m7 <= (NOT(s) AND x7) OR (s AND y7);
    END Behavior;

     
  • CG 2:54 pm on December 1, 2010 Permalink | Reply
    Tags: , block diagram/schematic, fpga, , ,   

    Pin Assignment for Altera DE2 

    Pin assignments for the toggle switches:

    Pin assignments for the LEDs

    Block Diagram/Schematic:

    Pin Assignment:

     
  • CG 11:45 am on November 30, 2010 Permalink | Reply
    Tags: fpga, , , usb-blaster driver,   

    Out of the box and works 

    Done doing one round of creating a new project and upload it to the fpga board, phew!
    I followed all the instructions in the manual book, including assigning real pins to the circuit

    installing usb-blaster driver on windows xp that running on top of virtual box running on top of mac os 😀

    and also switching pins of the device to check the truth table and see the light goes up. Fun 😀

     
  • CG 11:07 am on November 26, 2010 Permalink | Reply
    Tags: , cyclone ii, fpga   

    The new toy is now out of the box 

     
    • papanasya 1:56 pm on November 26, 2010 Permalink | Reply

      nah, ini mainan yg ingin kumainkan mbak dl tapi tak pernah ada yg mengizinkan mengopreknya… mesti punya stock banyak ktny kalo kamu yg ngopreknya … 😀

      • CG 8:56 pm on November 26, 2010 Permalink | Reply

        oh kalau gitu jangan berani2x ngoprek yang punya saya ya! 😀

    • Fernando Urbano 11:36 pm on November 29, 2010 Permalink | Reply

      I have the same board. It’s very nice. Also the book of Hamblen. How are your implementations of the multipliers? Greetings.

      • CG 8:38 am on November 30, 2010 Permalink | Reply

        hello fernando. i have just started reading the manuals and typed some simple vhdl codes to be loaded to the board 🙂 how is your implementation going?

        • Fernando Urbano 10:01 am on November 30, 2010 Permalink

          I finished the multiplier for GF(2^163). It´s implementation has good area and speed. Next step is design the GF(2^163) multiplier. I have the mathematic algorithm. Right now I’m working on the VHDL implementation and design.

        • Fernando Urbano 10:02 am on November 30, 2010 Permalink

          Sorry I want to told GF(2^233) implementation.

        • CG 10:07 am on November 30, 2010 Permalink

          wow great job. once you write a paper on that, i’d like to read 🙂
          btw are you doing this for thesis/dissertation?

        • CG 10:10 am on November 30, 2010 Permalink

          one more thing: is the architecture/algorithm different for GF(2^163) and GF(2^233) implementation?

    • Fernando Urbano 12:43 pm on December 6, 2010 Permalink | Reply

      Yes, I’m doing this for master’s thesis and also I’m using the same architecture and I hope finishing soon the 233 bits multiplier. If you know or if you implemented an algorith for 233 bits in normal basis, I’ll be very grateful if you tell me which maybe I can implemment it too. Greetings and good job.

      • CG 2:04 pm on December 6, 2010 Permalink | Reply

        wow. a great job for master’s thesis, good luck 🙂 yes i’ll share mostly my work in this blog and also will tell you if i happen implementing 233bits in normal basis. and i would like to read your papers and thesis too if possible since what we’re doing is very similar 🙂 thank you 🙂

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