## Simple Finite State Machine

A good article about Finite State Machine here.

• #### zakimath 2:08 pm on July 31, 2012 Permalink | Reply

Wah, itu menarik sekali untuk dibahas lho, apalagi dari sisi matematisnya, bisa sampe menggunakan teori kategori dan fungtor, coba tanya bu Intan… 🙂

## LUT-based multiplier with FSM

— FSM for changing input A and B (4bits)
— that will be input to multiplier
— CG – March 2011

library ieee ;
use ieee.std_logic_1164.all;

—————————————————–

entity FSM_CG is
port(
clock: in std_logic;
reset: in std_logic;
portAA: out std_logic_vector(3 downto 0);
portBB: out std_logic_vector(3 downto 0);
portCC: out std_logic_vector(3 downto 0);
portU: out std_logic_vector(3 downto 0);
portV: out std_logic_vector(3 downto 0);
portW: out std_logic_vector(3 downto 0);
portA: out std_logic_vector(3 downto 0);
portB: out std_logic_vector(3 downto 0);
portC: out std_logic_vector(3 downto 0)
);
end FSM_CG;

—————————————————–

architecture fsm of FSM_CG is
component LUT_MUL_BR_CG
port (
clk0 : in std_logic;
x, y: in std_logic_vector(3 downto 0);
z: out std_logic_vector(3 downto 0);
portu, portv, portw: out std_logic_vector(3 downto 0);
porta, portb, portc: out std_logic_vector(3 downto 0)
);
end component;

type state_type is (S0, S1, S2, S3, S4);
signal next_state, current_state: state_type;
signal A : std_logic_vector(3 downto 0);
signal B : std_logic_vector(3 downto 0);
signal C : std_logic_vector(3 downto 0);
begin
state_reg: process(clock, reset)
begin

if (reset=’1′) then
current_state <= S0;
elsif (clock’event and clock=’1′) then
current_state <= next_state;
end if;

end process;

— cocurrent process#2: combinational logic
comb_logic: process(current_state, clock)
begin
case current_state is

when S0 =>
A <= "0111";
B <= "0000";
next_state <= S1;
when S1 =>
A <= "0111";
B <= "0011";
next_state <= S2;
when S2 =>
A <= "0100";
B <= "0011";
next_state <= S3;
when S3 =>
A <= "0101";
B <= "0101";
next_state <= S4;
when S4 =>
A <= "0100";
B <= "0101";
next_state <= S1;
end case;
end process;
portAA <= A;
portBB <= B;
portCC <= C;

lutmulx: LUT_MUL_BR_CG port map(clock, a, b, c, portU, portV, portW, portA, portB, portC);

end fsm;

## Simple FSM

—————————————————–
— FSM for multiplier
— CG – 21 Jan 2011
—————————————————–

library ieee ;
use ieee.std_logic_1164.all;

—————————————————–

entity fsm_multiplierCG_1 is
port(
A0,A1,A2,A3: in bit_vector(1 downto 0);
opA : out bit_vector(1 downto 0);
clock: in std_logic;
reset: in std_logic
);
end fsm_multiplierCG_1;

—————————————————–

architecture FSM of fsm_multiplierCG_1 is

— define the states of FSM model

type state_type is (S0, S1, S2, S3);
signal next_state, current_state: state_type;

begin

— cocurrent process#1: state registers
state_reg: process(clock, reset)
begin

if (reset=’1′) then
current_state <= S0;
elsif (clock’event and clock=’1′) then
current_state <= next_state;
end if;

end process;

— cocurrent process#2: combinational logic
comb_logic: process(current_state, clock)
begin

— use case statement to show the
— state transistion

case current_state is

when S0 => opA <= A0;
next_state <= S1;

when S1 => opA <= A1;
next_state <= S2;

when S2 => opA <= A2;
next_state <= S3;

when S3 => opA <= A3;
next_state <= S0;

end case;

end process;

end FSM;

—————————————————–

c
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