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  • CG 7:02 pm on October 4, 2010 Permalink | Reply
    Tags: 299 bit, , hardware design, , shift register,   

    Shift-register 299-bit 

    The previous problem about 299-xor seemed to be related to port using. big number of ports cannot be declared in parallel.

    Today I learned to design a shift register that fits. Thank you, Guru 🙂

    library ieee;
    use ieee.std_logic_1164.all;

    entity regs is
    port (clock, Ain, Bin : in std_logic;
    Aout, Bout, Cout : out std_logic;
    shift_in: in std_logic);

    end entity regs;

    architecture rtl of regs is
    signal flag: std_logic;
    signal a, b, c: std_logic_vector(298 downto 0);
    flag <= clock and shift_in;
    if rising_edge(flag) then
    Aout <= a(298);
    Bout <= b(298);
    for N in 298 downto 1 loop
    a(N) <= A(N-1);
    b(N) <= B(N-1);
    end loop;
    a(0) <= Ain;
    b(0) <= Bin;
    end if;
    end process;
    end architecture rtl;

    • Budi Rahardjo 4:41 am on October 5, 2010 Permalink | Reply

      Lesson learned: sometimes we are faced with practical consideration(s) that we have to do unnecessary house keeping. In this particular case we have to take care of inputing data to the circuit. We cannot enter the data just like in software (“A = 55”) but we have to enter it serially due to (number of) pin limitation.

      Once the data is in the circuit, we then use it. And there where the fun begins 🙂

      Fortunately, you don’t have to deal with full custom design issues (like finding the most efficient placement and routing). 🙂 Phew …

      • CG 9:16 am on October 5, 2010 Permalink | Reply

        i still think that hw implementation is a whole lot more difficult than sw implementation.

        now we have the registers, so the fun shall begin? 🙂 without involving placement and routing my brain is already going to explode! finish multiplication in both ground and extension field, and fits, would make me really happy for now 🙂

    • Grow XL 10:41 am on June 1, 2013 Permalink | Reply

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  • CG 7:41 am on August 14, 2010 Permalink | Reply
    Tags: digital signature, , hardware design,   

    Now reading 

    A Low-Power VHDL Design for an Elliptic Curve Digital Signature Chip – Richard Schroeppel, Cheryl Beaver, and Timothy Draelos – Cryptography and Information Systems Surety Department, September 2002

  • CG 7:15 pm on May 1, 2010 Permalink | Reply
    Tags: 2^m, Agnew, , hardware design, , ,   

    Now reading 

    1. Arithmetic Operations in GF(2^m), G.B. Agnew, T. Beth, R.C. Mullin and Scott A. Vanstone, Journal of Cryptology, 1993.
    2. VLSI Designs for Multiplication over Finite Fields GF(2^m), Eduardo D. Mastrovito.
    • Fernando Urbano 2:28 am on December 10, 2010 Permalink | Reply

      Hello. I need to ask you for a favor. I had been looking for these papers (from above) I’ll be very grateful if you can send it to my e-mail. Thanks!

      • CG 4:56 am on December 10, 2010 Permalink | Reply

        ok i will send them to your email 🙂

    • Fernando Urbano 9:43 pm on December 10, 2010 Permalink | Reply

      Thanks, my e-mail is: faurbano@gmail.com.

    • rohani syawaliah 10:16 pm on December 15, 2010 Permalink | Reply

      postingannya walaupun saya nggak ngeh apa yang kamu baca itu

      ternyata dengan cara seperti ini memberikan manfaat juga ya buat orang laen?

      bagus banget

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