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  • CG 12:09 pm on October 13, 2010 Permalink | Reply
    Tags: , hardware simulation, , waveform   

    13bit adder 

    Don’t laugh. I’m still doing this and I want to make sure this is documented and can be easily use later for reference.


    library ieee;
    use ieee.std_logic_1164.all;

    entity adder13bit is
    port (clock, Ain, Bin : in std_logic;
    Aout, Bout, Cout : out std_logic;
    shift_in: in std_logic);
    end entity adder13bit;

    architecture rtl of adder13bit is
    signal flag: std_logic;
    signal a, b, c: std_logic_vector(12 downto 0);
    begin
    process(clock)
    begin
    flag <= clock and shift_in;
    if rising_edge(flag) then
    Aout <= a(12);
    Bout <= b(12);
    for N in 12 downto 1 loop
    a(N) <= A(N-1);
    b(N) <= B(N-1);
    end loop;
    a(0) <= Ain;
    b(0) <= Bin;
    end if;

    for N in 12 downto 0 loop
    c(N) <= A(N) xor B(N);
    Cout <= c(N);
    end loop;
    end process;
    end architecture rtl;

     
    • Budi Rahardjo 4:41 am on October 14, 2010 Permalink | Reply

      Good. Tapi formating program VHDL nya kok kacau. WordPress gak support VHDL?

      • CG 2:48 pm on October 14, 2010 Permalink | Reply

        iya gak support. kalau lyx sih support VHDL, yay 🙂

  • CG 10:22 am on June 11, 2010 Permalink | Reply
    Tags: , hardware simulation, , ,   

    with other clause error in quartus, why? 

    This simple multiplexer code in vhdl generates error:

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    
    entity MuxCG is
      port (Sel: in std_logic_vector(0 to 1);
      A, B, C, D: in std_logic_vector(0 to 3);
      Y:  out std_logic_vector(0 to 3));
    end MuxCG;
    
    architecture MuxCGArch of MuxCG is
    begin
      Y <= A when Sel = "00" else
           B when Sel = "01" else
           C when Sel = "10" else
           D when others;
    end MuxCGArch;
    

    Error (10500): VHDL syntax error at MuxCG.vhd(15) near text “others”;  expecting “(“, or an identifier (“others” is a reserved keyword), or  unary operator

    Still cannot fix this.

     
    • Bobby 11:05 am on June 12, 2010 Permalink | Reply

      don’t ask me

    • bang 7:10 pm on November 1, 2013 Permalink | Reply

      have a solution??? I same problem .. i crazy
      response my email please

      • elis 8:55 pm on January 31, 2014 Permalink | Reply

        I had the same problem, I was using two single apostrophes instead of one double. They often look very similar in the type-fonts used in programming. Now for example: ” =/ ”.
        So DOUBLE quotation mark.

        • CG 12:25 pm on February 2, 2014 Permalink

          ok thx 🙂

  • CG 3:50 pm on May 28, 2010 Permalink | Reply
    Tags: , hardware simulation,   

    Simulating classic multiplication with reduction 

    A = 10101010
    B = 10001111
    P = 00011011

    C = AxB mod P = 00011010

     
  • CG 2:40 pm on May 26, 2010 Permalink | Reply
    Tags: , hardware simulation, ,   

    Simulating classic multiplication 

    Classic multiplicationinvolves two steps: polynomial multiplication and reduction modulo an irreducible polynomial. This only tests 8 bits polynomial multiplication.

    The code is a modification from here

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    use work.classic_multiplier_parameters.all;

    entity classic_multiplication is
    port (
    a, b: in std_logic_vector(M-1 downto 0);
    c: out std_logic_vector(M-1 downto 0);
    d: out std_logic_vector(2*M-2 downto 0)
    );
    end classic_multiplication;

    architecture simple of classic_multiplication is
    component poly_multiplier port (
    a, b: in std_logic_vector(M-1 downto 0);
    d: out std_logic_vector(2*M-2 downto 0) );
    end component;

    -- component poly_reducer port (
    -- d: in std_logic_vector(2*M-2 downto 0);
    -- c: out std_logic_vector(M-1 downto 0));
    -- end component;

    -- signal d: std_logic_vector(2*M-2 downto 0);

    begin

    inst_mult: poly_multiplier port map(a => a, b => b, d => d);
    -- inst_reduc: poly_reducer port map(d => d, c => c);
    end simple;

    A=10101010
    B=10001111
    D = A.B without reduction = 101001100000110

    Next will be simulation the polynomial reduction.
    Question:
    Why the implementation of this book uses x^4+x^3+x+1 as the irreducible polynomial? Why don’t they use this list?

     
    • waskita 7:50 pm on May 26, 2010 Permalink | Reply

      Quartus? kapan nih masuk FPGA?

      • CG 3:59 am on May 27, 2010 Permalink | Reply

        ternyata kata promotor cukup sampe level RTL aja. tapi udah males pake modelsim, jadi pake quartus aja 🙂

  • CG 8:56 am on May 24, 2010 Permalink | Reply
    Tags: hardware simulation, ,   

    wait statement error in quartus 

    Mentioned here that:

    The Quartus® II software supports only a single VHDL wait-until statement in a process. Other VHDL wait constructs such as wait-for statements, or processes with more than one wait statement, are not synthesizable.

    Useful links:

    1. Table of Quartus II support for sequential statements
    2. A synthesizable delay generator instead of ‘wait for statement’
    3. Some discussions about this issues here and here
     
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