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  • CG 7:21 pm on March 3, 2011 Permalink | Reply
    Tags: clk, clock, hardware, , , ,   

    LUT-based multiplier with no clk 

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  • CG 11:55 am on March 3, 2011 Permalink | Reply
    Tags: component, hardware, , , ,   

    Implementing LUT-based multiplier as component 

    LUT_MUL_BR_CG.vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

    entity LUT_MUL_BR_CG is
    port (
    clk0 : in std_logic;
    x, y: in std_logic_vector(3 downto 0);
    z: out std_logic_vector(3 downto 0);
    portu, portv, portw: out std_logic_vector(3 downto 0);
    porta, portb, portc: out std_logic_vector(3 downto 0)
    );
    end LUT_MUL_BR_CG;

    architecture rtl of LUT_MUL_BR_CG is
    component LUT_BR
    port (
    clk : in std_logic;
    a, b: in std_logic_vector(3 downto 0);
    c: out std_logic_vector(3 downto 0);
    porta, portb, portc: out std_logic_vector(3 downto 0)
    );
    end component;

    signal u : std_logic_vector(3 downto 0);
    signal v : std_logic_vector(3 downto 0);
    signal w : std_logic_vector(3 downto 0);
    begin

    u <= x;
    v <= y;
    lutmul: lut_br port map(clk0, u, v, w, porta, portb, portc);
    z <= w;
    portu <= u;
    portv <= v;
    portw <= w; end rtl;

    LUT_BR.vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity LUT_BR is
    port (
    clk: in std_logic;
    a, b: in std_logic_vector(3 downto 0);
    c: buffer std_logic_vector(3 downto 0);
    porta, portb, portk, portc: out std_logic_vector(3 downto 0)
    );
    end entity LUT_BR;

    architecture behavioral of LUT_BR is
    component adder_mod_m_CG
    port (
    x, y: in std_logic_vector(3 downto 0);
    addb_sub: in std_logic;
    z: buffer std_logic_vector(3 downto 0)
    );
    end component;

    signal z : std_logic := ‘0’;
    signal i : std_logic_vector(3 downto 0);
    signal j : std_logic_vector(3 downto 0);
    signal k : std_logic_vector(3 downto 0);

    begin
    process(clk)
    begin
    if clk’event and clk = ‘1’ then
    case a is
    when "0001" => i <= "0000";
    when "0010" => i <= "0001";
    when "0011" => i <= "0011";
    when "0100" => i <= "0010";
    when "0101" => i <= "0110";
    when "0110" => i <= "0100";
    when "0111" => i <= "0101";
    when others => i <= "0000";
    end case;
    case b is
    when "0001" => j <= "0000";
    when "0010" => j <= "0001";
    when "0011" => j <= "0011";
    when "0100" => j <= "0010";
    when "0101" => j <= "0110";
    when "0110" => j <= "0100";
    when "0111" => j <= "0101";
    when others => j <= "0000";
    end case;
    case k is
    when "0000" => c <= "0001";
    when "0001" => c <= "0010";
    when "0010" => c <= "0100";
    when "0011" => c <= "0011";
    when "0100" => c <= "0110";
    when "0101" => c <= "0111";
    when "0110" => c <= "0101";
    when others => c <= "0000";
    end case;
    end if;
    end process;
    porta <= a;
    portb <= b;
    portk <= k;
    portc <= c;
    adderku: adder_mod_m_CG port map (i, j, z, k);

    end architecture behavioral;

    add_mod_m_CG.vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

    entity adder_mod_m_CG is
    port (
    x, y: in std_logic_vector(3 downto 0);
    addb_sub: in std_logic;
    z: out std_logic_vector(3 downto 0)
    );
    end adder_mod_m_CG;

    architecture rtl of adder_mod_m_CG is
    constant M: std_logic_vector(3 downto 0) := conv_std_logic_vector(7, 4);
    signal long_x, xor_y, sum1, long_z1, xor_m, sum2: std_logic_vector(4 downto 0);
    signal c1, c2, sel: std_logic;
    signal z1, z2: std_logic_vector(3 downto 0);

    begin

    long_x <= ‘0’ & x;
    xor_gates1: for i in 0 to 3 generate
    xor_y(i) <= y(i) xor addb_sub;
    end generate;
    xor_y(4) <= ‘0’;
    sum1 <= addb_sub + long_x + xor_y;
    c1 <= sum1(4);
    z1 <= sum1(3 downto 0);
    long_z1 <= ‘0’ & z1;
    xor_gates2: for i in 0 to 3 generate
    xor_m(i) <= m(i) xor not(addb_sub);
    end generate;
    xor_m(4) <= ‘0’;
    sum2 <= not(addb_sub) + long_z1 + xor_m;
    c2 <= sum2(4);
    z2 <= sum2(3 downto 0);
    sel <= (not(addb_sub) and (c1 or c2)) or (addb_sub and not(c1));
    with sel select z <= z1 when ‘0’, z2 when others;

    end rtl;

     
  • CG 2:54 pm on December 1, 2010 Permalink | Reply
    Tags: , block diagram/schematic, , hardware, ,   

    Pin Assignment for Altera DE2 

    Pin assignments for the toggle switches:

    Pin assignments for the LEDs

    Block Diagram/Schematic:

    Pin Assignment:

     
  • CG 11:45 am on November 30, 2010 Permalink | Reply
    Tags: , hardware, , usb-blaster driver,   

    Out of the box and works 

    Done doing one round of creating a new project and upload it to the fpga board, phew!
    I followed all the instructions in the manual book, including assigning real pins to the circuit

    installing usb-blaster driver on windows xp that running on top of virtual box running on top of mac os 😀

    and also switching pins of the device to check the truth table and see the light goes up. Fun 😀

     
  • CG 4:47 pm on November 17, 2010 Permalink | Reply
    Tags: hardware, , , , ,   

    LUT and Tristate buffer 


    library ieee;
    use ieee.std_logic_1164.all;

    entity lutmulCGver2 is
    port (
    clk : in std_logic;
    e : in std_logic;
    r : in std_logic;
    a, b: in std_logic_vector(3 downto 0);
    c: out std_logic_vector(3 downto 0);
    i, j, k : out std_logic_vector(3 downto 0);
    enA, enB, enC : in std_logic
    );
    end entity lutmulCGver2;

    architecture behavioral of lutmulCGver2 is
    -- signal i : integer range 0 to 6:=0;
    -- signal j : integer range 0 to 6:=0;
    signal tribus : std_logic_vector ( 3 downto 0 );
    signal enable : std_logic:='0';
    type alog is array (0 to 2**3 - 2) of std_logic_vector(3 downto 0);
    constant my_alog : alog := (
    0 => "0001",
    1 => "0010",
    2 => "0100",
    3 => "0011",
    4 => "0110",
    5 => "1111",
    6 => "0101");

    type log is array (1 to 2**3 - 1) of std_logic_vector(3 downto 0);
    -- type log is array (1 to 2**3 - 1) of integer;
    constant my_log : log := (
    1 => "0000",
    2 => "0001",
    3 => "0011",
    4 => "0010",
    5 => "0110",
    6 => "0100",
    7 => "0101");

    begin

    process(enA, enB, a, b)
    begin
    if enA = '1' then
    tribus <= a;
    elsif enB = '1' then
    tribus <= b;
    else
    tribus <= "ZZZZ";
    end if;
    end process;

    process(enC)
    begin
    if enC = '1' then
    c <= "0000";
    end case;
    end if;
    -- k <= (i xor j) xor "1011"; -- xor untuk mereduksi, tapi hanya
    berlaku untuk kalau generatornya x atau x+1
    end process;
    end architecture behavioral;

     
    • Budi Rahardjo 4:59 pm on November 17, 2010 Permalink | Reply

      good stuff (sambil belum dibaca tea :))

      • CG 5:08 pm on November 17, 2010 Permalink | Reply

        halah, padahal mau nanya, udah bener belum waveformsnya?

  • CG 6:22 pm on November 2, 2010 Permalink | Reply
    Tags: hardware, , ,   

    More tristate buffer 


    library IEEE;
    use IEEE.STD_LOGIC_1164.all;

    entity tristate is
    generic( width : integer := 7 );
    port ( enA, enB, enC : in std_logic;
    A, B: in std_logic_vector( width downto 0);
    C : out std_logic_vector( width downto 0)
    );
    end tristate;

    architecture rtl of tristate is
    signal tribus : std_logic_vector ( width downto 0 );
    begin
    process(enA, enB, A, B)
    begin
    if enA = '1' then
    tribus <= A;
    elsif enB = '1' then
    tribus <= B;
    else
    tribus <= "ZZZZZZZZ";
    end if;

    end process;

    process(enC)
    begin
    if enC = '1' then
    C <= tribus;
    end if;
    end process;
    end rtl;

     
  • CG 9:55 pm on October 29, 2010 Permalink | Reply
    Tags: hardware, , , ,   

    Tristate buffer 


    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;

    ENTITY bidir IS
    PORT(
    bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
    oe, clk : IN STD_LOGIC;
    inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    outp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
    END bidir;

    ARCHITECTURE maxpld OF bidir IS
    SIGNAL a : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores
    -- value from input.
    SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores
    BEGIN -- feedback value.
    PROCESS(clk)
    BEGIN
    IF clk = '1' AND clk'EVENT THEN -- Creates the flipflops
    a <= inp;
    outp <= b;
    END IF;
    END PROCESS;
    PROCESS (oe, bidir) -- Behavioral representation
    BEGIN -- of tri-states.
    IF( oe = '0') THEN
    bidir <= "ZZZZZZZZ";
    b <= bidir;
    ELSE
    bidir <= a;
    b <= bidir;
    END IF;
    END PROCESS;
    END maxpld;

     

     
    • Budi Rahardjo 12:11 am on October 30, 2010 Permalink | Reply

      Ok I can see that the tri-state is happening. Try this approach with your design and see if it can utilize tri-state in sharing the look-up table.

      • CG 5:51 am on October 30, 2010 Permalink | Reply

        haih, bikin tri-state aja susah gini ya 😀

  • CG 2:30 pm on October 21, 2010 Permalink | Reply
    Tags: , hardware, , , register,   

    Adder with register 


    library ieee;
    use ieee.std_logic_1164.all;

    entity adder2bitwithregjuga is
    port
    (clock: in std_logic;
    Ain: in std_logic;
    Bin: in std_logic;
    shift: in std_logic;
    CI: in std_logic;
    S : out std_logic_vector(1 downto 0);
    C0: out std_logic);
    end adder2bitwithregjuga;

    architecture arch of adder2bitwithregjuga is
    -- Specify the Full Adder subcircuit
    component Full_Adder
    port
    (AI,BI,CYI: in std_logic;
    SUM, CYO :out std_logic);
    end component;

    --Reserve a few signals for internal connections
    --signal CY0, CY1, CY2: bit;
    signal flag: std_logic;
    signal CY0: std_logic;
    signal A,B : std_logic_vector(1 downto 0);
    begin
    FA0: Full_Adder port map (A(0), B(0), CI, S(0), CY0);
    FA1: Full_Adder port map (A(1), B(1), CY0, S(1), C0);
    process(clock)
    begin
    flag <= clock and shift;
    if rising_edge(flag) then
    A(1) <= A(0);
    A(0) <= Ain;
    B(1) <= B(0);
    B(0) <= Bin;
    end if;
    end process;

    end arch;

    entity Full_Adder is
    port
    (AI,BI,CYI: in bit;
    SUM, CYO : out bit);
    end Full_Adder;

    architecture FA of Full_Adder is
    component Half_Adder
    port
    (W,X: in bit;
    Y,Z: out bit);
    end component;
    signal Y0,Z0,Z1: bit;
    begin
    HA0: Half_Adder port map(AI, BI, Y0, Z0);
    HA1: Half_Adder port map(CYI, Y0, SUM, Z1);
    CYO <= Z0 or Z1;
    end FA;

    entity Half_Adder is
    port
    (W,X: in bit;
    Y,Z: out bit);
    end Half_Adder;

    architecture HA of Half_Adder is
    begin
    Y <= W xor X; -- This is the sum bit
    Z <= W and X; -- This is the carry bit
    end HA;

     
    • Bobby 4:46 pm on October 21, 2010 Permalink | Reply

      HORRROOOORRR

    • Budi Rahardjo 2:03 pm on October 23, 2010 Permalink | Reply

      liat tuh di kodenya sampe ada yang ketawa (smiley)… he he he

      • CG 6:38 pm on October 23, 2010 Permalink | Reply

        itu bukan smile tapi lagi teriak “HORRROOOORRR! ” hihihihihi

  • CG 7:02 pm on October 4, 2010 Permalink | Reply
    Tags: 299 bit, hardware, , , shift register,   

    Shift-register 299-bit 

    The previous problem about 299-xor seemed to be related to port using. big number of ports cannot be declared in parallel.

    Today I learned to design a shift register that fits. Thank you, Guru 🙂


    library ieee;
    use ieee.std_logic_1164.all;

    entity regs is
    port (clock, Ain, Bin : in std_logic;
    Aout, Bout, Cout : out std_logic;
    shift_in: in std_logic);

    end entity regs;

    architecture rtl of regs is
    signal flag: std_logic;
    signal a, b, c: std_logic_vector(298 downto 0);
    begin
    process(clock)
    begin
    flag <= clock and shift_in;
    if rising_edge(flag) then
    Aout <= a(298);
    Bout <= b(298);
    for N in 298 downto 1 loop
    a(N) <= A(N-1);
    b(N) <= B(N-1);
    end loop;
    a(0) <= Ain;
    b(0) <= Bin;
    end if;
    end process;
    end architecture rtl;

     
    • Budi Rahardjo 4:41 am on October 5, 2010 Permalink | Reply

      Lesson learned: sometimes we are faced with practical consideration(s) that we have to do unnecessary house keeping. In this particular case we have to take care of inputing data to the circuit. We cannot enter the data just like in software (“A = 55”) but we have to enter it serially due to (number of) pin limitation.

      Once the data is in the circuit, we then use it. And there where the fun begins 🙂

      Fortunately, you don’t have to deal with full custom design issues (like finding the most efficient placement and routing). 🙂 Phew …

      • CG 9:16 am on October 5, 2010 Permalink | Reply

        i still think that hw implementation is a whole lot more difficult than sw implementation.

        now we have the registers, so the fun shall begin? 🙂 without involving placement and routing my brain is already going to explode! finish multiplication in both ground and extension field, and fits, would make me really happy for now 🙂

    • Grow XL 10:41 am on June 1, 2013 Permalink | Reply

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  • CG 5:35 pm on October 1, 2010 Permalink | Reply
    Tags: hardware, , ,   

    Adder 299bit – too many to fit in the selected device 

    if the adder cannot fit in, how to make an elliptic curve point multiplier can?

     
    • asp 12:53 pm on October 2, 2010 Permalink | Reply

      Kayaknya dibiarin dulu saja, terusin tidak masalah. Adder kan sebetulnya tidak harus keluar pin-nya.
      Kan hanya salah satu blok diagram dalam chipnya. Sekarang ke multiplier…

    • CG 6:02 pm on October 3, 2010 Permalink | Reply

      maybe i need the full version of quartus.

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