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  • CG 6:39 pm on December 30, 2010 Permalink | Reply
    Tags: , , multiplexer, ,   

    3 bit 5-to-1 mux 



    --CG praktikum lagi
    --Dec 30th 2010
    --3 bit 5-to-1 mux

    library ieee;
    use ieee.std_logic_1164.all;

    entity LabExCG6 is
    port (--u, v, w, x, y : in std_logic_vector(2 downto 0);
    -- s : in std_logic_vector(2 downto 0);
    -- m : out std_logic_vector(2 downto 0)
    u0, u1, u2 : in bit;
    v0, v1, v2 : in bit;
    w0, w1, w2 : in bit;
    x0, x1, x2 : in bit;
    y0, y1, y2 : in bit;
    s0, s1, s2 : in bit;
    m0, m1, m2 : out bit
    );

    end LabExCG6;

    architecture Behavior of LabExCG6 is
    component MUX_3_BIT_2_TO_1
    port
    (--x,y: in std_logic_vector(2 downto 0);
    --s: in std_logic_vector(2 downto 0);
    --m: out std_logic_vector(2 downto 0)
    a0, a1, a2, b0, b1, b2 : in bit;
    sel : in bit;
    m_out0, m_out1, m_out2 : out bit
    );
    end component;
    signal m00, m01, m02, m10, m11, m12, m20, m21, m22: bit;
    begin
    MUX0: MUX_3_BIT_2_TO_1 port map (u0, u1, u2, v0, v1, v2, s0, m00, m01, m02);
    MUX1: MUX_3_BIT_2_TO_1 port map (w0, w1, w2, x0, x1, x2, s0, m10, m11, m12);
    MUX2: MUX_3_BIT_2_TO_1 port map (m00, m01, m02, m10, m11, m12, s1, m20, m21, m22);
    MUX3: MUX_3_BIT_2_TO_1 port map (m20, m21, m22, y0, y1, y2, s2, m0, m1, m2);
    -- MUX0: MUX_3_BIT_2_TO_1 port map (u, v, s(0), m1);
    -- MUX1: MUX_3_BIT 2_TO_1 port map (w, x, s(0), m2);
    -- MUX2: MUX_3_BIT_2_TO_1 port map (m1, m2, s(1), m3);
    -- MUX3: MUX_3_BIT_2_TO_1 port map (m3, y, s(2), m);
    end Behavior;

    --entity LabExCG6 is
    entity MUX_3_BIT_2_TO_1 is
    port
    ( --a, b: in std_logic_vector(2 downto 0);
    a0, a1, a2, b0, b1, b2 : in bit;
    sel : in bit;
    -- m_out : out std_logic_vector(2 downto 1));
    m_out0, m_out1, m_out2 : out bit);
    end MUX_3_BIT_2_TO_1;
    --end LabExCG6;

    architecture M3BIT2TO1 of MUX_3_BIT_2_TO_1 is
    --architecture Behavior of LabExCG6 is
    component MUX_2_TO_1
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end component;
    begin
    MUX0: MUX_2_TO_1 port map (a0, b0, sel, m_out0);
    MUX1: MUX_2_TO_1 port map (a1, b1, sel, m_out1);
    MUX2: MUX_2_TO_1 port map (a2, b2, sel, m_out2);
    -- MUX0: MUX_2_TO_1 port map (a(0), b(0), sel, m_out(0));
    -- MUX1: MUX_2_TO_1 port map (a(1), b(1), sel, m_out(1));
    -- MUX2: MUX_2_TO_1 port map (a(2), b(2), sel, m_out(2));
    end M3BIT2TO1;
    --end Behavior;

    entity MUX_2_TO_1 is
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end MUX_2_TO_1;

    architecture M2TO1 of MUX_2_TO_1 is
    begin
    m <= (NOT(s) AND x) OR (s AND y);
    end M2TO1;

     

    this is the revised code. much simpler

    library ieee;
    use ieee.std_logic_1164.all;

    entity LabExCG6 is
    port (u, v, w, x, y : in bit_vector(2 downto 0);
    s : in bit_vector(2 downto 0);
    m : out bit_vector(2 downto 0)
    );
    end LabExCG6;

    architecture Behavior of LabExCG6 is
    component MUX_3_BIT_2_TO_1
    port
    (a,b: in bit_vector(2 downto 0);
    sel: in bit;
    m_out: out bit_vector(2 downto 0)
    );
    end component;
    signal m0, m1, m2: bit_vector(2 downto 0);
    begin
    MUX0: MUX_3_BIT_2_TO_1 port map (u, v, s(0), m0);
    MUX1: MUX_3_BIT_2_TO_1 port map (w, x, s(0), m1);
    MUX2: MUX_3_BIT_2_TO_1 port map (m0, m1, s(1), m2);
    MUX3: MUX_3_BIT_2_TO_1 port map (m2, y, s(2), m);
    end Behavior;

    entity MUX_3_BIT_2_TO_1 is
    port
    ( a, b: in bit_vector(2 downto 0);
    sel : in bit;
    m_out : out bit_vector(2 downto 0));
    end MUX_3_BIT_2_TO_1;

    architecture M3BIT2TO1 of MUX_3_BIT_2_TO_1 is
    component MUX_2_TO_1
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end component;
    begin
    MUX0: MUX_2_TO_1 port map (a(0), b(0), sel, m_out(0));
    MUX1: MUX_2_TO_1 port map (a(1), b(1), sel, m_out(1));
    MUX2: MUX_2_TO_1 port map (a(2), b(2), sel, m_out(2));
    end M3BIT2TO1;

    entity MUX_2_TO_1 is
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end MUX_2_TO_1;

    architecture M2TO1 of MUX_2_TO_1 is
    begin
    m <= (NOT(s) AND x) OR (s AND y);
    end M2TO1;

     
    • CG 6:44 pm on December 30, 2010 Permalink | Reply

      still cannot understand why this doesnt work using std_logic_vector?

      • CG 9:16 pm on December 30, 2010 Permalink | Reply

        you should use bit_vector instead of std_logic_vector

  • CG 4:53 pm on December 30, 2010 Permalink | Reply
    Tags: , , multiplexer, ,   

    3 bit 2-to-1 mux 


    --CG praktikum lagi
    --Dec 29th 2010
    --3 bit 2-to-1 mux

    library ieee;
    use ieee.std_logic_1164.all;

    entity LabExCG5 is
    port
    ( a0, a1, a2, b0, b1, b2 : in bit;
    sel : in bit;
    m_out0, m_out1, m_out2 : out bit);
    end LabExCG5;

    architecture Behavior of LabExCG5 is
    component MUX_2_TO_1
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end component;
    begin
    MUX0: MUX_2_TO_1 port map (a0, b0, sel, m_out0);
    MUX1: MUX_2_TO_1 port map (a1, b1, sel, m_out1);
    MUX2: MUX_2_TO_1 port map (a2, b2, sel, m_out2);
    end Behavior;

    entity MUX_2_TO_1 is
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end MUX_2_TO_1;

     

    architecture M2TO1 of MUX_2_TO_1 is
    begin
    m <= (NOT(s) AND x) OR (s AND y);
    end M2TO1;

    revised version (watch the difference, especially the RTL):


    library ieee;
    use ieee.std_logic_1164.all;

    entity LabExCG5 is
    port
    ( a, b: in bit_vector(2 downto 0);
    sel : in bit;
    m_out : out bit_vector(2 downto 0));
    end LabExCG5;

    architecture Behavior of LabExCG5 is
    component MUX_2_TO_1
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end component;
    begin
    MUX0: MUX_2_TO_1 port map (a(0), b(0), sel, m_out(0));
    MUX1: MUX_2_TO_1 port map (a(1), b(1), sel, m_out(1));
    MUX2: MUX_2_TO_1 port map (a(2), b(2), sel, m_out(2));
    end Behavior;

    entity MUX_2_TO_1 is
    port
    (x,y: in bit;
    s: in bit;
    m: out bit);
    end MUX_2_TO_1;

     

    architecture M2TO1 of MUX_2_TO_1 is
    begin
    m <= (NOT(s) AND x) OR (s AND y);
    end M2TO1;

     
    • CG 5:06 pm on December 30, 2010 Permalink | Reply

      why this code doesnt work? because of the vectors?

      library ieee;
      use ieee.std_logic_1164.all;

      entity LabExCG5 is
      port
      ( a, b: in std_logic_vector(2 downto 0);
      sel : in bit;
      m_out : out std_logic_vector(2 downto 1));
      end LabExCG5;

      architecture Behavior of LabExCG5 is
      component MUX_2_TO_1
      port
      (x,y: in bit;
      s: in bit;
      m: out bit);
      end component;
      begin
      MUX0: MUX_2_TO_1 port map (a(0), b(0), sel, m_out(0));
      MUX1: MUX_2_TO_1 port map (a(1), b(1), sel, m_out(1));
      MUX2: MUX_2_TO_1 port map (a(2), b(2), sel, m_out(2));
      end Behavior;

      entity MUX_2_TO_1 is
      port
      (x,y: in bit;
      s: in bit;
      m: out bit);
      end MUX_2_TO_1;

      architecture M2TO1 of MUX_2_TO_1 is
      begin
      m <= (NOT(s) AND x) OR (s AND y);
      end M2TO1;

    • CG 5:07 pm on December 30, 2010 Permalink | Reply

      the error message is:
      Error (10381): VHDL Type Mismatch error at LabExCG5.vhd(52): indexed name returns a value whose type does not match “bit”, the type of the target expression

      • CG 10:33 pm on December 30, 2010 Permalink | Reply

        it solved by changing “std_logic_vector” into “bit_logic_vector”

  • CG 10:20 pm on December 6, 2010 Permalink | Reply
    Tags: , multiplexer, ,   

    5-to-1 multiplexer 

    Lab exercise:

    VHDL code:

    Pin planner:

     
  • CG 3:45 pm on December 3, 2010 Permalink | Reply
    Tags: , , multiplexer, mux,   

    8-bit 2-to-1 multiplexer 

    Laboratory Exercise:

    RTL View:

    VHDL Code:

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;

    -- Simple module that connects the SW switches to the LEDR lights
    ENTITY LabExCG2 IS
    PORT( x0, x1, x2, x3, x4, x5, x6, x7 : IN BIT;
    y0, y1, y2, y3, y4, y5, y6, y7 : IN BIT;
    s : IN BIT;
    m0, m1, m2, m3, m4, m5, m6, m7 : OUT BIT);
    END LabExCG2;

    ARCHITECTURE Behavior OF LabExCG2 IS
    BEGIN
    m0 <= (NOT(s) AND x0) OR (s AND y0);
    m1 <= (NOT(s) AND x1) OR (s AND y1);
    m2 <= (NOT(s) AND x2) OR (s AND y2);
    m3 <= (NOT(s) AND x3) OR (s AND y3);
    m4 <= (NOT(s) AND x4) OR (s AND y4);
    m5 <= (NOT(s) AND x5) OR (s AND y5);
    m6 <= (NOT(s) AND x6) OR (s AND y6);
    m7 <= (NOT(s) AND x7) OR (s AND y7);
    END Behavior;

     
  • CG 10:22 am on June 11, 2010 Permalink | Reply
    Tags: , , multiplexer, ,   

    with other clause error in quartus, why? 

    This simple multiplexer code in vhdl generates error:

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    
    entity MuxCG is
      port (Sel: in std_logic_vector(0 to 1);
      A, B, C, D: in std_logic_vector(0 to 3);
      Y:  out std_logic_vector(0 to 3));
    end MuxCG;
    
    architecture MuxCGArch of MuxCG is
    begin
      Y <= A when Sel = "00" else
           B when Sel = "01" else
           C when Sel = "10" else
           D when others;
    end MuxCGArch;
    

    Error (10500): VHDL syntax error at MuxCG.vhd(15) near text “others”;  expecting “(“, or an identifier (“others” is a reserved keyword), or  unary operator

    Still cannot fix this.

     
    • Bobby 11:05 am on June 12, 2010 Permalink | Reply

      don’t ask me

    • bang 7:10 pm on November 1, 2013 Permalink | Reply

      have a solution??? I same problem .. i crazy
      response my email please

      • elis 8:55 pm on January 31, 2014 Permalink | Reply

        I had the same problem, I was using two single apostrophes instead of one double. They often look very similar in the type-fonts used in programming. Now for example: ” =/ ”.
        So DOUBLE quotation mark.

        • CG 12:25 pm on February 2, 2014 Permalink

          ok thx 🙂

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