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  • CG 2:36 pm on May 26, 2011 Permalink | Reply
    Tags: multiplier, ,   

    24629 lines of code 

    after this one works, next will be KOA.

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    • amirul 2:38 pm on May 26, 2011 Permalink | Reply

      bejar memahami code” script..

    • Bobby Adi Prabowo 4:51 pm on May 26, 2011 Permalink | Reply

      file nya dikit ya, cuma 3, ga aneh jumlah kode bisa segitu. apalagi liat klo liat kode “if” statement nya, repetitif banget

      • CG 7:04 pm on May 26, 2011 Permalink | Reply

        lha iya byk line of code nya wong isinya LUT 😀 ini di posting hanya untuk dokumentasi aja dan logbook kemajuan penelitian, dan gak semua code full dikeluarin, nanti ada yang nyabot disertasi gue gawat :))

      • ali 11:23 pm on June 25, 2011 Permalink | Reply

        hi..i am from pakistan.can u make a code in vhdl of cryptography in fpga which i can simulate on xilinx or modelsim

  • CG 9:27 pm on March 4, 2011 Permalink | Reply
    Tags: , , multiplier, ,   

    LUT-based multiplier with FSM 

    — FSM for changing input A and B (4bits)
    — that will be input to multiplier
    — CG – March 2011

    library ieee ;
    use ieee.std_logic_1164.all;

    —————————————————–

    entity FSM_CG is
    port(
    clock: in std_logic;
    reset: in std_logic;
    portAA: out std_logic_vector(3 downto 0);
    portBB: out std_logic_vector(3 downto 0);
    portCC: out std_logic_vector(3 downto 0);
    portU: out std_logic_vector(3 downto 0);
    portV: out std_logic_vector(3 downto 0);
    portW: out std_logic_vector(3 downto 0);
    portA: out std_logic_vector(3 downto 0);
    portB: out std_logic_vector(3 downto 0);
    portC: out std_logic_vector(3 downto 0)
    );
    end FSM_CG;

    —————————————————–

    architecture fsm of FSM_CG is
    component LUT_MUL_BR_CG
    port (
    clk0 : in std_logic;
    x, y: in std_logic_vector(3 downto 0);
    z: out std_logic_vector(3 downto 0);
    portu, portv, portw: out std_logic_vector(3 downto 0);
    porta, portb, portc: out std_logic_vector(3 downto 0)
    );
    end component;

    type state_type is (S0, S1, S2, S3, S4);
    signal next_state, current_state: state_type;
    signal A : std_logic_vector(3 downto 0);
    signal B : std_logic_vector(3 downto 0);
    signal C : std_logic_vector(3 downto 0);
    begin
    state_reg: process(clock, reset)
    begin

    if (reset=’1′) then
    current_state <= S0;
    elsif (clock’event and clock=’1′) then
    current_state <= next_state;
    end if;

    end process;

    — cocurrent process#2: combinational logic
    comb_logic: process(current_state, clock)
    begin
    case current_state is

    when S0 =>
    A <= "0111";
    B <= "0000";
    next_state <= S1;
    when S1 =>
    A <= "0111";
    B <= "0011";
    next_state <= S2;
    when S2 =>
    A <= "0100";
    B <= "0011";
    next_state <= S3;
    when S3 =>
    A <= "0101";
    B <= "0101";
    next_state <= S4;
    when S4 =>
    A <= "0100";
    B <= "0101";
    next_state <= S1;
    end case;
    end process;
    portAA <= A;
    portBB <= B;
    portCC <= C;

    lutmulx: LUT_MUL_BR_CG port map(clock, a, b, c, portU, portV, portW, portA, portB, portC);

    end fsm;

     
  • CG 7:21 pm on March 3, 2011 Permalink | Reply
    Tags: clk, clock, , , multiplier, ,   

    LUT-based multiplier with no clk 

     
  • CG 11:55 am on March 3, 2011 Permalink | Reply
    Tags: component, , , multiplier, ,   

    Implementing LUT-based multiplier as component 

    LUT_MUL_BR_CG.vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

    entity LUT_MUL_BR_CG is
    port (
    clk0 : in std_logic;
    x, y: in std_logic_vector(3 downto 0);
    z: out std_logic_vector(3 downto 0);
    portu, portv, portw: out std_logic_vector(3 downto 0);
    porta, portb, portc: out std_logic_vector(3 downto 0)
    );
    end LUT_MUL_BR_CG;

    architecture rtl of LUT_MUL_BR_CG is
    component LUT_BR
    port (
    clk : in std_logic;
    a, b: in std_logic_vector(3 downto 0);
    c: out std_logic_vector(3 downto 0);
    porta, portb, portc: out std_logic_vector(3 downto 0)
    );
    end component;

    signal u : std_logic_vector(3 downto 0);
    signal v : std_logic_vector(3 downto 0);
    signal w : std_logic_vector(3 downto 0);
    begin

    u <= x;
    v <= y;
    lutmul: lut_br port map(clk0, u, v, w, porta, portb, portc);
    z <= w;
    portu <= u;
    portv <= v;
    portw <= w; end rtl;

    LUT_BR.vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity LUT_BR is
    port (
    clk: in std_logic;
    a, b: in std_logic_vector(3 downto 0);
    c: buffer std_logic_vector(3 downto 0);
    porta, portb, portk, portc: out std_logic_vector(3 downto 0)
    );
    end entity LUT_BR;

    architecture behavioral of LUT_BR is
    component adder_mod_m_CG
    port (
    x, y: in std_logic_vector(3 downto 0);
    addb_sub: in std_logic;
    z: buffer std_logic_vector(3 downto 0)
    );
    end component;

    signal z : std_logic := ‘0’;
    signal i : std_logic_vector(3 downto 0);
    signal j : std_logic_vector(3 downto 0);
    signal k : std_logic_vector(3 downto 0);

    begin
    process(clk)
    begin
    if clk’event and clk = ‘1’ then
    case a is
    when "0001" => i <= "0000";
    when "0010" => i <= "0001";
    when "0011" => i <= "0011";
    when "0100" => i <= "0010";
    when "0101" => i <= "0110";
    when "0110" => i <= "0100";
    when "0111" => i <= "0101";
    when others => i <= "0000";
    end case;
    case b is
    when "0001" => j <= "0000";
    when "0010" => j <= "0001";
    when "0011" => j <= "0011";
    when "0100" => j <= "0010";
    when "0101" => j <= "0110";
    when "0110" => j <= "0100";
    when "0111" => j <= "0101";
    when others => j <= "0000";
    end case;
    case k is
    when "0000" => c <= "0001";
    when "0001" => c <= "0010";
    when "0010" => c <= "0100";
    when "0011" => c <= "0011";
    when "0100" => c <= "0110";
    when "0101" => c <= "0111";
    when "0110" => c <= "0101";
    when others => c <= "0000";
    end case;
    end if;
    end process;
    porta <= a;
    portb <= b;
    portk <= k;
    portc <= c;
    adderku: adder_mod_m_CG port map (i, j, z, k);

    end architecture behavioral;

    add_mod_m_CG.vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

    entity adder_mod_m_CG is
    port (
    x, y: in std_logic_vector(3 downto 0);
    addb_sub: in std_logic;
    z: out std_logic_vector(3 downto 0)
    );
    end adder_mod_m_CG;

    architecture rtl of adder_mod_m_CG is
    constant M: std_logic_vector(3 downto 0) := conv_std_logic_vector(7, 4);
    signal long_x, xor_y, sum1, long_z1, xor_m, sum2: std_logic_vector(4 downto 0);
    signal c1, c2, sel: std_logic;
    signal z1, z2: std_logic_vector(3 downto 0);

    begin

    long_x <= ‘0’ & x;
    xor_gates1: for i in 0 to 3 generate
    xor_y(i) <= y(i) xor addb_sub;
    end generate;
    xor_y(4) <= ‘0’;
    sum1 <= addb_sub + long_x + xor_y;
    c1 <= sum1(4);
    z1 <= sum1(3 downto 0);
    long_z1 <= ‘0’ & z1;
    xor_gates2: for i in 0 to 3 generate
    xor_m(i) <= m(i) xor not(addb_sub);
    end generate;
    xor_m(4) <= ‘0’;
    sum2 <= not(addb_sub) + long_z1 + xor_m;
    c2 <= sum2(4);
    z2 <= sum2(3 downto 0);
    sel <= (not(addb_sub) and (c1 or c2)) or (addb_sub and not(c1));
    with sel select z <= z1 when ‘0’, z2 when others;

    end rtl;

     
  • CG 3:15 pm on February 25, 2011 Permalink | Reply
    Tags: finite field, look up table, , multiplier, ,   

    4 bits LUT-based multiplier 

    LUT_BR. vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity LUT_BR is
    port (
    clk : in std_logic;
    a, b: in std_logic_vector(3 downto 0);
    c: out std_logic_vector(3 downto 0);
    porti : out std_logic_vector(3 downto 0);
    portj : out std_logic_vector(3 downto 0);
    portk : out std_logic_vector(3 downto 0)
    );
    end entity LUT_BR;

    architecture behavioral of LUT_BR is
    component adder_mod_m_CG
    port (
    x, y: in std_logic_vector(3 downto 0);
    addb_sub: in std_logic;
    z: buffer std_logic_vector(3 downto 0)
    );
    end component;

    signal z : std_logic := ‘0’;
    signal i : std_logic_vector(3 downto 0);
    signal j : std_logic_vector(3 downto 0);
    signal k : std_logic_vector(3 downto 0);

    begin

    process (clk)
    begin
    if clk’event and clk = ‘1’ then
    case a is
    when "0001" => i <= "0000";
    when "0010" => i <= "0001";
    when "0011" => i <= "0011";
    when "0100" => i <= "0010";
    when "0101" => i <= "0110";
    when "0110" => i <= "0100";
    when "0111" => i <= "0101";
    when others => i <= "0000";
    end case;
    case b is
    when "0001" => j <= "0000";
    when "0010" => j <= "0001";
    when "0011" => j <= "0011";
    when "0100" => j <= "0010";
    when "0101" => j <= "0110";
    when "0110" => j <= "0100";
    when "0111" => j <= "0101";
    when others => j <= "0000";
    end case;
    case k is
    when "0000" => c <= "0001";
    when "0001" => c <= "0010";
    when "0010" => c <= "0100";
    when "0011" => c <= "0011";
    when "0100" => c <= "0110";
    when "0101" => c <= "0111";
    when "0110" => c <= "0101";
    when others => c <= "0000";
    end case;
    end if;

    end process;

    adderku: adder_mod_m_CG port map (i, j, z, k);
    porti <= i;
    portj <= j;
    portk <= k;

    end architecture behavioral;

    adder_mod_m_CG.vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

    entity adder_mod_m_CG is
    port (
    x, y: in std_logic_vector(3 downto 0);
    addb_sub: in std_logic;
    z: out std_logic_vector(3 downto 0)
    );
    end adder_mod_m_CG;

    architecture rtl of adder_mod_m_CG is
    constant M: std_logic_vector(3 downto 0) := conv_std_logic_vector(7, 4);
    signal long_x, xor_y, sum1, long_z1, xor_m, sum2: std_logic_vector(4 downto 0);
    signal c1, c2, sel: std_logic;
    signal z1, z2: std_logic_vector(3 downto 0);

    begin

    long_x <= ‘0’ & x;
    xor_gates1: for i in 0 to 3 generate
    xor_y(i) <= y(i) xor addb_sub;
    end generate;
    xor_y(4) <= ‘0’;
    sum1 <= addb_sub + long_x + xor_y;
    c1 <= sum1(4);
    z1 <= sum1(3 downto 0);
    long_z1 <= ‘0’ & z1;
    xor_gates2: for i in 0 to 3 generate
    xor_m(i) <= m(i) xor not(addb_sub);
    end generate;
    xor_m(4) <= ‘0’;
    sum2 <= not(addb_sub) + long_z1 + xor_m;
    c2 <= sum2(4);
    z2 <= sum2(3 downto 0);
    sel <= (not(addb_sub) and (c1 or c2)) or (addb_sub and not(c1));
    with sel select z <= z1 when ‘0’, z2 when others;

    end rtl;

    Pair programming always works 🙂 Thank you Guru 🙂

     
  • CG 9:23 pm on January 9, 2011 Permalink | Reply
    Tags: , multiplier   

    Back to paper and pencil 

     
  • CG 9:13 pm on August 22, 2010 Permalink | Reply
    Tags: multiplier,   

    Now reading 

    Finished reading about multiplier over GF(2^n) – polynomial bases.
    Now moving on to multiplier for Optimal Normal Basis Type II.
    1. An Efficient Optimal Normal Basis Type II Multiplier, B. Sunar, C. K. Koc
    2. Brief Contributions – An Efficient Optimal Normal Basis Type II Multiplier, B. Sunar, C. K. Koc

    Next will be designing multiplier for composite field and implement it in vhdl.

     
    • Fernando Urbano 10:09 pm on November 7, 2010 Permalink | Reply

      Greetings, I tried to implemented these multiplier for 233 bits, a Type II ONB, but I hadn’t success. Could you did it? If so, could you tell me how? Thanks!!!! Very nice blog I like it a lot of.

      • CG 5:25 am on November 8, 2010 Permalink | Reply

        hello fernando, thx for visiting the blog. i’m now still trying to implement multiplier for 299bits, using PB. maybe after successfully implement PB version (assuming that it’s easier than ONB II) then i will start using Type II ONB.

        do you implement it using vhdl too?

    • Fernando Urbano 12:00 pm on November 8, 2010 Permalink | Reply

      yes, I did. But I think that something ws wrong with the permutage stage (changing base) to reconvert the result at the ONB again. I think that is very large multiplier compare with others. What kind of PB muliplier are you trying to implement?

      • CG 12:13 pm on November 8, 2010 Permalink | Reply

        we have developed conversion algorithm from PB – ONB1 and vice versa but not yet for PB – ONB2. what is your consideration of using ONB2? i’m trying to implement the two-step classic multiplication. i need a classic multiplication method to be compared to multiplication for composite field in PB representation. do you have any experiences with composite field?

    • Fernando Urbano 11:37 pm on November 12, 2010 Permalink | Reply

      We considere, OB2 because it’s the only one in these base from the five (m = 163, 233, 283, 409, 571) recommended by NIST for elliptic curve digital signature algorithm.

  • CG 4:56 pm on August 21, 2010 Permalink | Reply
    Tags: , , multiplier,   

    Weekend Read 

    Hardware Implementation of Finite-Field Arithmetic – Jean Pierre Deschamps, Jose Luis Imana, Gustavo D. Sutter, Chapter 7.

    Going to learn about all multiplier for finite fields. And think how can a non-finite field multiplier be applied for finite field applications.

     
  • CG 6:18 pm on June 1, 2010 Permalink | Reply
    Tags: , galois fields, , multiplier   

    Now reading: 

    Mastrovito Edoardo, “VLSI Architectures for Computations in Galois Fields”, PhD Thesis, 1991.

    Conclusion:

    is there anything-has-never-been-done-as-phd-thesis left so i can finish mine? aarrrgghhhh

     
  • CG 10:38 pm on May 28, 2010 Permalink | Reply
    Tags: , , hybrid multiplier, multiplier   

    Hybrid multipliers 

    Have read this, and these are several notes:

    1. Hybrid multiplier is application of bit parallel architectures to arithmetic in the subfield GF(2^n) and of a bit serial structures to arithmetic in the extension field GF((2^n)^m)
    2. The major advantage of hybrid architecture is that the number clock cycles for one multiplication is reduced by a factor of n. The hybrid multiplier explores thus the time-space trade-off paradigm, where the degree of the trade-off (performance versus complexity) is determined by the field decomposition n\cdot m
     
    • mahinair2003 12:46 am on June 16, 2011 Permalink | Reply

      Hi CG: I am Mahesh new to this community. I found some interesting discussions about ONB I and II multipliers. I was trying to make a 163 bit ONB multiplier. I tried to understand the paper from KOC and Sunar also the paper from M. A Hasan. but the multiplication matrix they talk about is so crazy. did u make a 163 bit NB multiplier???? Can you share the vhdl code if you have???
      cheers

c
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