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  • CG 2:36 pm on May 26, 2011 Permalink | Reply
    Tags: , quartus,   

    24629 lines of code 

    after this one works, next will be KOA.

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    • amirul 2:38 pm on May 26, 2011 Permalink | Reply

      bejar memahami code” script..

    • Bobby Adi Prabowo 4:51 pm on May 26, 2011 Permalink | Reply

      file nya dikit ya, cuma 3, ga aneh jumlah kode bisa segitu. apalagi liat klo liat kode “if” statement nya, repetitif banget

      • CG 7:04 pm on May 26, 2011 Permalink | Reply

        lha iya byk line of code nya wong isinya LUT 😀 ini di posting hanya untuk dokumentasi aja dan logbook kemajuan penelitian, dan gak semua code full dikeluarin, nanti ada yang nyabot disertasi gue gawat :))

      • ali 11:23 pm on June 25, 2011 Permalink | Reply

        hi..i am from pakistan.can u make a code in vhdl of cryptography in fpga which i can simulate on xilinx or modelsim

  • CG 10:07 am on May 19, 2011 Permalink | Reply
    Tags: , quartus,   

    Generic map in vhdl now works 

    Yay! I’ve got useful advices from the previous posting, and now it works 🙂 Thanks 🙂

    All I need to do is adding this code in separated file, and then compile.

    library ieee;
    use ieee. std_logic_1164.all;

    entity para_binary_counter is
    generic (WIDTH: natural);
    port(
    clk, reset: in std_logic;
    q: out std_logic_vector(WIDTH-1 downto 0)
    );
    end para_binary_counter;

    architecture arch of para_binary_counter is
    begin
    end arch;

    Now it works 🙂

     
    • amirul 10:30 am on May 23, 2011 Permalink | Reply

      it is very dificult.. i want try carefully

    • ali 11:22 pm on June 25, 2011 Permalink | Reply

      hi..i am from pakistan.can u make a code in vhdl of cryptography in fpga which i can simulate on xilinx or modelsim

    • aya 9:46 pm on August 27, 2013 Permalink | Reply

      Can you help mee with this lease ?? Use Verilog HDL to design a 2-bit comparator using 2×4 decoders and any gates required.

  • CG 3:14 pm on May 18, 2011 Permalink | Reply
    Tags: , quartus,   

    Generic map error in VHDL 

    Still can’t make this work.


    library ieee;
    use ieee. std_logic_1164.all;

    entity generic_demo is
    port(
    clk, reset: in std_logic;
    q_4: out std_logic_vector(3 downto 0);
    q_12: out std_logic_vector(11 downto 0)
    );
    end generic_demo;

    architecture vhdl_87_arch of generic_demo is
    component para_binary_counter
    generic (WIDTH: natural);
    port(
    clk, reset: in std_logic;
    q: out std_logic_vector(WIDTH-1 downto 0)
    );
    end component;

    begin
    four_bit: para_binary_counter
    generic map (WIDTH=>4)
    port map(clk=>clk, reset=>reset, q=>q_4);
    twe_bit: para_binary_counter
    generic map (WIDTH=>12)
    port map(clk=>clk, reset=>reset, q=>q_12);
    end vhdl_87_arch;

    Error message:

     
    • Lieven Lemiengre 9:17 pm on May 18, 2011 Permalink | Reply

      You need to provide an implementation for “para_binary_counter” and make sure it it compiled before you compile this file.

      • CG 10:17 am on May 19, 2011 Permalink | Reply

        thx so much, it now works 🙂

    • Dio Gratia 6:30 am on May 19, 2011 Permalink | Reply

      What Lieven said:

      % ghdl -a ( -a in the analyze command)
      % ghdl -e generic_demo (-e is the elaborate command)
      foo.vhdl:22:1:warning: component instance “four_bit” is not bound
      foo.vhdl:12:14:warning: (in default configuration of generic_demo(vhdl_87_arch))
      foo.vhdl:25:1:warning: component instance “twe_bit” is not bound
      foo.vhdl:12:14:warning: (in default configuration of generic_demo(vhdl_87_arch))

      See IEEE 1076-2008

      14.4.2.8 Component declarations

      Elaboration of a component declaration has no effect other than to create a template for instantiating component instances.

      14.5.4 Component instantiation statements

      Elaboration of a component instantiation statement that instantiates a component declaration has no effect unless the component instance is either fully bound to a design entity defined by an entity declaration and architecture body or bound to a configuration of such a design entity. If a component instance is so bound,

      Error conditions are explicit in IEEE 1076. ‘no effect’ was taken as sufficient to indicate a warning here by Tristan Gingold, the author of ghdl.

      13.5 Order of analysis

      The rules defining the order in which design units can be analyzed are direct consequences of the visibility rules. In particular

      a) A primary unit whose name is referenced within a given design unit shall be analyzed prior to the
      analysis of the given design unit.

      b) A primary unit shall be analyzed prior to the analysis of any corresponding secondary unit.

      The use of ‘shall’ indicates you may not proceed. (And the LRM doesn’t appear to explicitly state that).

      The use of ‘Error’ on the part of Quartus II tools appears to be based on tool architecture (tools calling tools and deciding to abort the process) rather than VHDL compliance.

      This particular issue is based on the VHDL standard and not the Quartus tool.

      • CG 10:18 am on May 19, 2011 Permalink | Reply

        wow i didnt know that this thing is in IEEE docs, thx for pointing me this

    • Dio Gratia 6:39 am on May 19, 2011 Permalink | Reply

      GHDL for Mac OS X

      The mcode version of GHDL has been packaged for Mac OS X 10.5/10.6, i386 (32 bit). Installation requires administrative privilege for installing in /usr/local.

      A functional gtkwave waveform viewer can be obtained from the eng-osx project on Sourceforge. Alternatively with Xcode and Macports, installed, in a terminal window type:

      sudo port install gtkwave

      The build may be lengthy, 44 libraries plus gtkwave built from source and installed when starting from scratch.

      (I saw your were using a Macbook)

      • CG 10:20 am on May 19, 2011 Permalink | Reply

        i used gdhl and gtkwave a long time ago and already forgot evthing about them now, so I stick with quartus and now it works, thx so much 🙂

    • Ivan Montoya 11:07 pm on June 7, 2011 Permalink | Reply

      Change the name of project in a new project.

    • ayaa 9:47 pm on August 27, 2013 Permalink | Reply

      Can you help mee with this lease ?? Use Verilog HDL to design a 2-bit comparator using 2×4 decoders and any gates required.

      • aya 9:47 pm on August 27, 2013 Permalink | Reply

        Can you help mee with this lease ?? Use Verilog HDL to design a 2-bit comparator using 2×4 decoders and any gates required.

        • aya 10:01 pm on August 27, 2013 Permalink

          Can you help me with this lease ?? Use Verilog HDL to design a 2-bit comparator using 2×4 decoders and any gates required.

      • aya 10:01 pm on August 27, 2013 Permalink | Reply

        Can you help me with this lease ?? Use Verilog HDL to design a 2-bit comparator using 2×4 decoders and any gates required.

    • aya 9:48 pm on August 27, 2013 Permalink | Reply

      Can you help mee with this lease ?? Use Verilog HDL to design a 2-bit comparator using 2×4 decoders and any gates required.

    • aya 1:20 am on August 28, 2013 Permalink | Reply

      Can you help me with this please ?? Use Verilog HDL to design a 2-bit comparator using 2×4 decoders and any gates required.

  • CG 3:14 pm on April 19, 2011 Permalink | Reply
    Tags: , cyclone, , quartus   

    Logic Elements in Cyclone II 

    Some good references:

    1. http://idle-logic.com/2010/02/11/dissecting-the-cyclone-2-handbook-part1/
    2. http://www.cs.columbia.edu/~sedwards/classes/2011/4840/cyc2_cii5v1.pdf
    3. http://www.altera.com/literature/hb/cyc2/cyc2_cii5v1.pdf
    4. http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf
    5. http://www.altera.com/products/devices/cyclone2/features/cy2-features.html
    Note:
    Stratix Family is high-end FPGA while Cyclone Family is low-end FPGA (the mid-range FPGA is Arria).
     
  • CG 9:27 pm on March 4, 2011 Permalink | Reply
    Tags: , , , quartus,   

    LUT-based multiplier with FSM 

    — FSM for changing input A and B (4bits)
    — that will be input to multiplier
    — CG – March 2011

    library ieee ;
    use ieee.std_logic_1164.all;

    —————————————————–

    entity FSM_CG is
    port(
    clock: in std_logic;
    reset: in std_logic;
    portAA: out std_logic_vector(3 downto 0);
    portBB: out std_logic_vector(3 downto 0);
    portCC: out std_logic_vector(3 downto 0);
    portU: out std_logic_vector(3 downto 0);
    portV: out std_logic_vector(3 downto 0);
    portW: out std_logic_vector(3 downto 0);
    portA: out std_logic_vector(3 downto 0);
    portB: out std_logic_vector(3 downto 0);
    portC: out std_logic_vector(3 downto 0)
    );
    end FSM_CG;

    —————————————————–

    architecture fsm of FSM_CG is
    component LUT_MUL_BR_CG
    port (
    clk0 : in std_logic;
    x, y: in std_logic_vector(3 downto 0);
    z: out std_logic_vector(3 downto 0);
    portu, portv, portw: out std_logic_vector(3 downto 0);
    porta, portb, portc: out std_logic_vector(3 downto 0)
    );
    end component;

    type state_type is (S0, S1, S2, S3, S4);
    signal next_state, current_state: state_type;
    signal A : std_logic_vector(3 downto 0);
    signal B : std_logic_vector(3 downto 0);
    signal C : std_logic_vector(3 downto 0);
    begin
    state_reg: process(clock, reset)
    begin

    if (reset=’1′) then
    current_state <= S0;
    elsif (clock’event and clock=’1′) then
    current_state <= next_state;
    end if;

    end process;

    — cocurrent process#2: combinational logic
    comb_logic: process(current_state, clock)
    begin
    case current_state is

    when S0 =>
    A <= "0111";
    B <= "0000";
    next_state <= S1;
    when S1 =>
    A <= "0111";
    B <= "0011";
    next_state <= S2;
    when S2 =>
    A <= "0100";
    B <= "0011";
    next_state <= S3;
    when S3 =>
    A <= "0101";
    B <= "0101";
    next_state <= S4;
    when S4 =>
    A <= "0100";
    B <= "0101";
    next_state <= S1;
    end case;
    end process;
    portAA <= A;
    portBB <= B;
    portCC <= C;

    lutmulx: LUT_MUL_BR_CG port map(clock, a, b, c, portU, portV, portW, portA, portB, portC);

    end fsm;

     
  • CG 7:21 pm on March 3, 2011 Permalink | Reply
    Tags: clk, clock, , , , quartus,   

    LUT-based multiplier with no clk 

     
  • CG 11:55 am on March 3, 2011 Permalink | Reply
    Tags: component, , , , quartus,   

    Implementing LUT-based multiplier as component 

    LUT_MUL_BR_CG.vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

    entity LUT_MUL_BR_CG is
    port (
    clk0 : in std_logic;
    x, y: in std_logic_vector(3 downto 0);
    z: out std_logic_vector(3 downto 0);
    portu, portv, portw: out std_logic_vector(3 downto 0);
    porta, portb, portc: out std_logic_vector(3 downto 0)
    );
    end LUT_MUL_BR_CG;

    architecture rtl of LUT_MUL_BR_CG is
    component LUT_BR
    port (
    clk : in std_logic;
    a, b: in std_logic_vector(3 downto 0);
    c: out std_logic_vector(3 downto 0);
    porta, portb, portc: out std_logic_vector(3 downto 0)
    );
    end component;

    signal u : std_logic_vector(3 downto 0);
    signal v : std_logic_vector(3 downto 0);
    signal w : std_logic_vector(3 downto 0);
    begin

    u <= x;
    v <= y;
    lutmul: lut_br port map(clk0, u, v, w, porta, portb, portc);
    z <= w;
    portu <= u;
    portv <= v;
    portw <= w; end rtl;

    LUT_BR.vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity LUT_BR is
    port (
    clk: in std_logic;
    a, b: in std_logic_vector(3 downto 0);
    c: buffer std_logic_vector(3 downto 0);
    porta, portb, portk, portc: out std_logic_vector(3 downto 0)
    );
    end entity LUT_BR;

    architecture behavioral of LUT_BR is
    component adder_mod_m_CG
    port (
    x, y: in std_logic_vector(3 downto 0);
    addb_sub: in std_logic;
    z: buffer std_logic_vector(3 downto 0)
    );
    end component;

    signal z : std_logic := ‘0’;
    signal i : std_logic_vector(3 downto 0);
    signal j : std_logic_vector(3 downto 0);
    signal k : std_logic_vector(3 downto 0);

    begin
    process(clk)
    begin
    if clk’event and clk = ‘1’ then
    case a is
    when "0001" => i <= "0000";
    when "0010" => i <= "0001";
    when "0011" => i <= "0011";
    when "0100" => i <= "0010";
    when "0101" => i <= "0110";
    when "0110" => i <= "0100";
    when "0111" => i <= "0101";
    when others => i <= "0000";
    end case;
    case b is
    when "0001" => j <= "0000";
    when "0010" => j <= "0001";
    when "0011" => j <= "0011";
    when "0100" => j <= "0010";
    when "0101" => j <= "0110";
    when "0110" => j <= "0100";
    when "0111" => j <= "0101";
    when others => j <= "0000";
    end case;
    case k is
    when "0000" => c <= "0001";
    when "0001" => c <= "0010";
    when "0010" => c <= "0100";
    when "0011" => c <= "0011";
    when "0100" => c <= "0110";
    when "0101" => c <= "0111";
    when "0110" => c <= "0101";
    when others => c <= "0000";
    end case;
    end if;
    end process;
    porta <= a;
    portb <= b;
    portk <= k;
    portc <= c;
    adderku: adder_mod_m_CG port map (i, j, z, k);

    end architecture behavioral;

    add_mod_m_CG.vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

    entity adder_mod_m_CG is
    port (
    x, y: in std_logic_vector(3 downto 0);
    addb_sub: in std_logic;
    z: out std_logic_vector(3 downto 0)
    );
    end adder_mod_m_CG;

    architecture rtl of adder_mod_m_CG is
    constant M: std_logic_vector(3 downto 0) := conv_std_logic_vector(7, 4);
    signal long_x, xor_y, sum1, long_z1, xor_m, sum2: std_logic_vector(4 downto 0);
    signal c1, c2, sel: std_logic;
    signal z1, z2: std_logic_vector(3 downto 0);

    begin

    long_x <= ‘0’ & x;
    xor_gates1: for i in 0 to 3 generate
    xor_y(i) <= y(i) xor addb_sub;
    end generate;
    xor_y(4) <= ‘0’;
    sum1 <= addb_sub + long_x + xor_y;
    c1 <= sum1(4);
    z1 <= sum1(3 downto 0);
    long_z1 <= ‘0’ & z1;
    xor_gates2: for i in 0 to 3 generate
    xor_m(i) <= m(i) xor not(addb_sub);
    end generate;
    xor_m(4) <= ‘0’;
    sum2 <= not(addb_sub) + long_z1 + xor_m;
    c2 <= sum2(4);
    z2 <= sum2(3 downto 0);
    sel <= (not(addb_sub) and (c1 or c2)) or (addb_sub and not(c1));
    with sel select z <= z1 when ‘0’, z2 when others;

    end rtl;

     
  • CG 3:15 pm on February 25, 2011 Permalink | Reply
    Tags: finite field, look up table, , , quartus,   

    4 bits LUT-based multiplier 

    LUT_BR. vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity LUT_BR is
    port (
    clk : in std_logic;
    a, b: in std_logic_vector(3 downto 0);
    c: out std_logic_vector(3 downto 0);
    porti : out std_logic_vector(3 downto 0);
    portj : out std_logic_vector(3 downto 0);
    portk : out std_logic_vector(3 downto 0)
    );
    end entity LUT_BR;

    architecture behavioral of LUT_BR is
    component adder_mod_m_CG
    port (
    x, y: in std_logic_vector(3 downto 0);
    addb_sub: in std_logic;
    z: buffer std_logic_vector(3 downto 0)
    );
    end component;

    signal z : std_logic := ‘0’;
    signal i : std_logic_vector(3 downto 0);
    signal j : std_logic_vector(3 downto 0);
    signal k : std_logic_vector(3 downto 0);

    begin

    process (clk)
    begin
    if clk’event and clk = ‘1’ then
    case a is
    when "0001" => i <= "0000";
    when "0010" => i <= "0001";
    when "0011" => i <= "0011";
    when "0100" => i <= "0010";
    when "0101" => i <= "0110";
    when "0110" => i <= "0100";
    when "0111" => i <= "0101";
    when others => i <= "0000";
    end case;
    case b is
    when "0001" => j <= "0000";
    when "0010" => j <= "0001";
    when "0011" => j <= "0011";
    when "0100" => j <= "0010";
    when "0101" => j <= "0110";
    when "0110" => j <= "0100";
    when "0111" => j <= "0101";
    when others => j <= "0000";
    end case;
    case k is
    when "0000" => c <= "0001";
    when "0001" => c <= "0010";
    when "0010" => c <= "0100";
    when "0011" => c <= "0011";
    when "0100" => c <= "0110";
    when "0101" => c <= "0111";
    when "0110" => c <= "0101";
    when others => c <= "0000";
    end case;
    end if;

    end process;

    adderku: adder_mod_m_CG port map (i, j, z, k);
    porti <= i;
    portj <= j;
    portk <= k;

    end architecture behavioral;

    adder_mod_m_CG.vhdl

    library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

    entity adder_mod_m_CG is
    port (
    x, y: in std_logic_vector(3 downto 0);
    addb_sub: in std_logic;
    z: out std_logic_vector(3 downto 0)
    );
    end adder_mod_m_CG;

    architecture rtl of adder_mod_m_CG is
    constant M: std_logic_vector(3 downto 0) := conv_std_logic_vector(7, 4);
    signal long_x, xor_y, sum1, long_z1, xor_m, sum2: std_logic_vector(4 downto 0);
    signal c1, c2, sel: std_logic;
    signal z1, z2: std_logic_vector(3 downto 0);

    begin

    long_x <= ‘0’ & x;
    xor_gates1: for i in 0 to 3 generate
    xor_y(i) <= y(i) xor addb_sub;
    end generate;
    xor_y(4) <= ‘0’;
    sum1 <= addb_sub + long_x + xor_y;
    c1 <= sum1(4);
    z1 <= sum1(3 downto 0);
    long_z1 <= ‘0’ & z1;
    xor_gates2: for i in 0 to 3 generate
    xor_m(i) <= m(i) xor not(addb_sub);
    end generate;
    xor_m(4) <= ‘0’;
    sum2 <= not(addb_sub) + long_z1 + xor_m;
    c2 <= sum2(4);
    z2 <= sum2(3 downto 0);
    sel <= (not(addb_sub) and (c1 or c2)) or (addb_sub and not(c1));
    with sel select z <= z1 when ‘0’, z2 when others;

    end rtl;

    Pair programming always works 🙂 Thank you Guru 🙂

     
  • CG 2:43 pm on February 19, 2011 Permalink | Reply
    Tags: quartus, signal, variable,   

    Signal vs variable in VHDL 

    Signals are similar to hardware and are not updated until the end of a process. Variables are immediately updated. Xilinx recommends using signals for hardware descriptions; however, variables allow quick simulation.

    If several values are assigned to a signal in one process, only the final value is used. When a value is assigned to a variable, the assignment takes place immediately. A variable maintains its value until a new value specified.

    Signal:
    Library IEEE;
    use IEEE.std_logic_1164.all;
    entity xor_sig is

    port (A, B, C: in STD_LOGIC;
    X, Y: out STD_LOGIC);
    end xor_sig;

    architecture SIG_ARCH of xor_sig is
    signal D: STD_LOGIC;
    begin
    SIG:process (A,B,C)
    begin
    D <= A; — ignored !!
    X <= C xor D;
    D <= B; — overrides !!
    Y <= C xor D;
    end process;
    end SIG_ARCH;

    Variable:
    Library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all;

    entity xor_var is
    port (A, B, C: in STD_LOGIC;
    X, Y: out STD_LOGIC);
    end xor_var;

    architecture VAR_ARCH of xor_var is
    begin

    VAR:process (A,B,C)
    variable D: STD_LOGIC;
    begin
    D := A;
    X <= C xor D;
    D := B;
    Y <= C xor D;
    end process;
    end VAR_ARCH;

    Useful links:

    1. http://www.xilinx.com/itp/xilinx4/data/docs/sim/coding4.html
    2. http://www.gmvhdl.com/signals.htm
     
    • Budi Rahardjo 3:58 pm on February 19, 2011 Permalink | Reply

      bagus untuk memahami semantics dari keduanya

      • CG 5:39 pm on February 19, 2011 Permalink | Reply

        liat deh hasilnya. kalau pake signal D -nya gak berubah walau di initiate ke A

  • CG 7:30 pm on January 21, 2011 Permalink | Reply
    Tags: , , quartus,   

    Simple FSM 

    —————————————————–
    — FSM for multiplier
    — CG – 21 Jan 2011
    —————————————————–

    library ieee ;
    use ieee.std_logic_1164.all;

    —————————————————–

    entity fsm_multiplierCG_1 is
    port(
    A0,A1,A2,A3: in bit_vector(1 downto 0);
    opA : out bit_vector(1 downto 0);
    clock: in std_logic;
    reset: in std_logic
    );
    end fsm_multiplierCG_1;

    —————————————————–

    architecture FSM of fsm_multiplierCG_1 is

    — define the states of FSM model

    type state_type is (S0, S1, S2, S3);
    signal next_state, current_state: state_type;

    begin

    — cocurrent process#1: state registers
    state_reg: process(clock, reset)
    begin

    if (reset=’1′) then
    current_state <= S0;
    elsif (clock’event and clock=’1′) then
    current_state <= next_state;
    end if;

    end process;

    — cocurrent process#2: combinational logic
    comb_logic: process(current_state, clock)
    begin

    — use case statement to show the
    — state transistion

    case current_state is

    when S0 => opA <= A0;
    next_state <= S1;

    when S1 => opA <= A1;
    next_state <= S2;

    when S2 => opA <= A2;
    next_state <= S3;

    when S3 => opA <= A3;
    next_state <= S0;

    end case;

    end process;

    end FSM;

    —————————————————–

     

     
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