8-bit 2-to-1 multiplexer

Laboratory Exercise:

RTL View:

VHDL Code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

-- Simple module that connects the SW switches to the LEDR lights
ENTITY LabExCG2 IS
PORT( x0, x1, x2, x3, x4, x5, x6, x7 : IN BIT;
y0, y1, y2, y3, y4, y5, y6, y7 : IN BIT;
s : IN BIT;
m0, m1, m2, m3, m4, m5, m6, m7 : OUT BIT);
END LabExCG2;

ARCHITECTURE Behavior OF LabExCG2 IS
BEGIN
m0 <= (NOT(s) AND x0) OR (s AND y0);
m1 <= (NOT(s) AND x1) OR (s AND y1);
m2 <= (NOT(s) AND x2) OR (s AND y2);
m3 <= (NOT(s) AND x3) OR (s AND y3);
m4 <= (NOT(s) AND x4) OR (s AND y4);
m5 <= (NOT(s) AND x5) OR (s AND y5);
m6 <= (NOT(s) AND x6) OR (s AND y6);
m7 <= (NOT(s) AND x7) OR (s AND y7);
END Behavior;

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