Classic multiplicationinvolves two steps: polynomial multiplication and reduction modulo an irreducible polynomial. This only tests 8 bits polynomial multiplication.

The code is a modification from here

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use work.classic_multiplier_parameters.all;

```
```entity classic_multiplication is

port (

a, b: in std_logic_vector(M-1 downto 0);

c: out std_logic_vector(M-1 downto 0);

d: out std_logic_vector(2*M-2 downto 0)

);

end classic_multiplication;

architecture simple of classic_multiplication is

component poly_multiplier port (

a, b: in std_logic_vector(M-1 downto 0);

d: out std_logic_vector(2*M-2 downto 0) );

end component;

-- component poly_reducer port (

-- d: in std_logic_vector(2*M-2 downto 0);

-- c: out std_logic_vector(M-1 downto 0));

-- end component;

-- signal d: std_logic_vector(2*M-2 downto 0);

begin

` inst_mult: poly_multiplier port map(a => a, b => b, d => d);`

-- inst_reduc: poly_reducer port map(d => d, c => c);

end simple;

A=10101010

B=10001111

D = A.B without reduction = 101001100000110

Next will be simulation the polynomial reduction.

Question:

Why the implementation of this book uses as the irreducible polynomial? Why don’t they use this list?

## mahinair2003 12:46 am

onJune 16, 2011 Permalink |Hi CG: I am Mahesh new to this community. I found some interesting discussions about ONB I and II multipliers. I was trying to make a 163 bit ONB multiplier. I tried to understand the paper from KOC and Sunar also the paper from M. A Hasan. but the multiplication matrix they talk about is so crazy. did u make a 163 bit NB multiplier???? Can you share the vhdl code if you have???

cheers