Back to VHDL

One of our papers is invited to an international journal, so in order to add new content of at least 30% to the conference version (further analysis, additional simulation/experimental results, detailed design/synthesis, further comparison with other related methods, a more elaborated discussion), we decided to do more exploration and experiments on composite field implementation with VHDL.

And I have to read this.

24629 lines of code

after this one works, next will be KOA.

PhD Life: 2 weeks before progress seminar

Perl scripting is very useful when you have to generate 8192 lines of code in VHDL.

Generic map in vhdl now works

Yay! I’ve got useful advices from the previous posting, and now it works 🙂 Thanks 🙂

All I need to do is adding this code in separated file, and then compile.

library ieee;
use ieee. std_logic_1164.all;

entity para_binary_counter is
generic (WIDTH: natural);
port(
clk, reset: in std_logic;
q: out std_logic_vector(WIDTH-1 downto 0)
);
end para_binary_counter;

architecture arch of para_binary_counter is
begin
end arch;


Now it works 🙂

Generic map error in VHDL

Still can’t make this work.


library ieee;
use ieee. std_logic_1164.all;

entity generic_demo is
port(
clk, reset: in std_logic;
q_4: out std_logic_vector(3 downto 0);
q_12: out std_logic_vector(11 downto 0)
);
end generic_demo;

architecture vhdl_87_arch of generic_demo is
component para_binary_counter
generic (WIDTH: natural);
port(
clk, reset: in std_logic;
q: out std_logic_vector(WIDTH-1 downto 0)
);
end component;

begin
four_bit: para_binary_counter
generic map (WIDTH=>4)
port map(clk=>clk, reset=>reset, q=>q_4);
twe_bit: para_binary_counter
generic map (WIDTH=>12)
port map(clk=>clk, reset=>reset, q=>q_12);
end vhdl_87_arch;


Error message:

LUT-based multiplier with FSM

— FSM for changing input A and B (4bits)
— that will be input to multiplier
— CG – March 2011

library ieee ;
use ieee.std_logic_1164.all;

—————————————————–

entity FSM_CG is
port(
clock: in std_logic;
reset: in std_logic;
portAA: out std_logic_vector(3 downto 0);
portBB: out std_logic_vector(3 downto 0);
portCC: out std_logic_vector(3 downto 0);
portU: out std_logic_vector(3 downto 0);
portV: out std_logic_vector(3 downto 0);
portW: out std_logic_vector(3 downto 0);
portA: out std_logic_vector(3 downto 0);
portB: out std_logic_vector(3 downto 0);
portC: out std_logic_vector(3 downto 0)
);
end FSM_CG;

—————————————————–

architecture fsm of FSM_CG is
component LUT_MUL_BR_CG
port (
clk0 : in std_logic;
x, y: in std_logic_vector(3 downto 0);
z: out std_logic_vector(3 downto 0);
portu, portv, portw: out std_logic_vector(3 downto 0);
porta, portb, portc: out std_logic_vector(3 downto 0)
);
end component;

type state_type is (S0, S1, S2, S3, S4);
signal next_state, current_state: state_type;
signal A : std_logic_vector(3 downto 0);
signal B : std_logic_vector(3 downto 0);
signal C : std_logic_vector(3 downto 0);
begin
state_reg: process(clock, reset)
begin

if (reset=’1′) then
current_state <= S0;
elsif (clock’event and clock=’1′) then
current_state <= next_state;
end if;

end process;

— cocurrent process#2: combinational logic
comb_logic: process(current_state, clock)
begin
case current_state is

when S0 =>
A <= "0111";
B <= "0000";
next_state <= S1;
when S1 =>
A <= "0111";
B <= "0011";
next_state <= S2;
when S2 =>
A <= "0100";
B <= "0011";
next_state <= S3;
when S3 =>
A <= "0101";
B <= "0101";
next_state <= S4;
when S4 =>
A <= "0100";
B <= "0101";
next_state <= S1;
end case;
end process;
portAA <= A;
portBB <= B;
portCC <= C;

lutmulx: LUT_MUL_BR_CG port map(clock, a, b, c, portU, portV, portW, portA, portB, portC);

end fsm;

LUT-based multiplier with no clk

Implementing LUT-based multiplier as component

LUT_MUL_BR_CG.vhdl

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity LUT_MUL_BR_CG is
port (
clk0 : in std_logic;
x, y: in std_logic_vector(3 downto 0);
z: out std_logic_vector(3 downto 0);
portu, portv, portw: out std_logic_vector(3 downto 0);
porta, portb, portc: out std_logic_vector(3 downto 0)
);
end LUT_MUL_BR_CG;

architecture rtl of LUT_MUL_BR_CG is
component LUT_BR
port (
clk : in std_logic;
a, b: in std_logic_vector(3 downto 0);
c: out std_logic_vector(3 downto 0);
porta, portb, portc: out std_logic_vector(3 downto 0)
);
end component;

signal u : std_logic_vector(3 downto 0);
signal v : std_logic_vector(3 downto 0);
signal w : std_logic_vector(3 downto 0);
begin

u <= x;
v <= y;
lutmul: lut_br port map(clk0, u, v, w, porta, portb, portc);
z <= w;
portu <= u;
portv <= v;
portw <= w; end rtl;

LUT_BR.vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity LUT_BR is
port (
clk: in std_logic;
a, b: in std_logic_vector(3 downto 0);
c: buffer std_logic_vector(3 downto 0);
porta, portb, portk, portc: out std_logic_vector(3 downto 0)
);
end entity LUT_BR;

architecture behavioral of LUT_BR is
component adder_mod_m_CG
port (
x, y: in std_logic_vector(3 downto 0);
addb_sub: in std_logic;
z: buffer std_logic_vector(3 downto 0)
);
end component;

signal z : std_logic := ‘0’;
signal i : std_logic_vector(3 downto 0);
signal j : std_logic_vector(3 downto 0);
signal k : std_logic_vector(3 downto 0);

begin
process(clk)
begin
if clk’event and clk = ‘1’ then
case a is
when "0001" => i <= "0000";
when "0010" => i <= "0001";
when "0011" => i <= "0011";
when "0100" => i <= "0010";
when "0101" => i <= "0110";
when "0110" => i <= "0100";
when "0111" => i <= "0101";
when others => i <= "0000";
end case;
case b is
when "0001" => j <= "0000";
when "0010" => j <= "0001";
when "0011" => j <= "0011";
when "0100" => j <= "0010";
when "0101" => j <= "0110";
when "0110" => j <= "0100";
when "0111" => j <= "0101";
when others => j <= "0000";
end case;
case k is
when "0000" => c <= "0001";
when "0001" => c <= "0010";
when "0010" => c <= "0100";
when "0011" => c <= "0011";
when "0100" => c <= "0110";
when "0101" => c <= "0111";
when "0110" => c <= "0101";
when others => c <= "0000";
end case;
end if;
end process;
porta <= a;
portb <= b;
portk <= k;
portc <= c;
adderku: adder_mod_m_CG port map (i, j, z, k);

end architecture behavioral;

add_mod_m_CG.vhdl

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity adder_mod_m_CG is
port (
x, y: in std_logic_vector(3 downto 0);
addb_sub: in std_logic;
z: out std_logic_vector(3 downto 0)
);
end adder_mod_m_CG;

architecture rtl of adder_mod_m_CG is
constant M: std_logic_vector(3 downto 0) := conv_std_logic_vector(7, 4);
signal long_x, xor_y, sum1, long_z1, xor_m, sum2: std_logic_vector(4 downto 0);
signal c1, c2, sel: std_logic;
signal z1, z2: std_logic_vector(3 downto 0);

begin

long_x <= ‘0’ & x;
xor_gates1: for i in 0 to 3 generate
xor_y(i) <= y(i) xor addb_sub;
end generate;
xor_y(4) <= ‘0’;
sum1 <= addb_sub + long_x + xor_y;
c1 <= sum1(4);
z1 <= sum1(3 downto 0);
long_z1 <= ‘0’ & z1;
xor_gates2: for i in 0 to 3 generate
xor_m(i) <= m(i) xor not(addb_sub);
end generate;
xor_m(4) <= ‘0’;
sum2 <= not(addb_sub) + long_z1 + xor_m;
c2 <= sum2(4);
z2 <= sum2(3 downto 0);
sel <= (not(addb_sub) and (c1 or c2)) or (addb_sub and not(c1));
with sel select z <= z1 when ‘0’, z2 when others;

end rtl;

4 bits LUT-based multiplier

LUT_BR. vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity LUT_BR is
port (
clk : in std_logic;
a, b: in std_logic_vector(3 downto 0);
c: out std_logic_vector(3 downto 0);
porti : out std_logic_vector(3 downto 0);
portj : out std_logic_vector(3 downto 0);
portk : out std_logic_vector(3 downto 0)
);
end entity LUT_BR;

architecture behavioral of LUT_BR is
component adder_mod_m_CG
port (
x, y: in std_logic_vector(3 downto 0);
addb_sub: in std_logic;
z: buffer std_logic_vector(3 downto 0)
);
end component;

signal z : std_logic := ‘0’;
signal i : std_logic_vector(3 downto 0);
signal j : std_logic_vector(3 downto 0);
signal k : std_logic_vector(3 downto 0);

begin

process (clk)
begin
if clk’event and clk = ‘1’ then
case a is
when "0001" => i <= "0000";
when "0010" => i <= "0001";
when "0011" => i <= "0011";
when "0100" => i <= "0010";
when "0101" => i <= "0110";
when "0110" => i <= "0100";
when "0111" => i <= "0101";
when others => i <= "0000";
end case;
case b is
when "0001" => j <= "0000";
when "0010" => j <= "0001";
when "0011" => j <= "0011";
when "0100" => j <= "0010";
when "0101" => j <= "0110";
when "0110" => j <= "0100";
when "0111" => j <= "0101";
when others => j <= "0000";
end case;
case k is
when "0000" => c <= "0001";
when "0001" => c <= "0010";
when "0010" => c <= "0100";
when "0011" => c <= "0011";
when "0100" => c <= "0110";
when "0101" => c <= "0111";
when "0110" => c <= "0101";
when others => c <= "0000";
end case;
end if;

end process;

adderku: adder_mod_m_CG port map (i, j, z, k);
porti <= i;
portj <= j;
portk <= k;

end architecture behavioral;

adder_mod_m_CG.vhdl

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity adder_mod_m_CG is
port (
x, y: in std_logic_vector(3 downto 0);
addb_sub: in std_logic;
z: out std_logic_vector(3 downto 0)
);
end adder_mod_m_CG;

architecture rtl of adder_mod_m_CG is
constant M: std_logic_vector(3 downto 0) := conv_std_logic_vector(7, 4);
signal long_x, xor_y, sum1, long_z1, xor_m, sum2: std_logic_vector(4 downto 0);
signal c1, c2, sel: std_logic;
signal z1, z2: std_logic_vector(3 downto 0);

begin

long_x <= ‘0’ & x;
xor_gates1: for i in 0 to 3 generate
xor_y(i) <= y(i) xor addb_sub;
end generate;
xor_y(4) <= ‘0’;
sum1 <= addb_sub + long_x + xor_y;
c1 <= sum1(4);
z1 <= sum1(3 downto 0);
long_z1 <= ‘0’ & z1;
xor_gates2: for i in 0 to 3 generate
xor_m(i) <= m(i) xor not(addb_sub);
end generate;
xor_m(4) <= ‘0’;
sum2 <= not(addb_sub) + long_z1 + xor_m;
c2 <= sum2(4);
z2 <= sum2(3 downto 0);
sel <= (not(addb_sub) and (c1 or c2)) or (addb_sub and not(c1));
with sel select z <= z1 when ‘0’, z2 when others;

end rtl;

Pair programming always works 🙂 Thank you Guru 🙂

Signal vs variable in VHDL

Signals are similar to hardware and are not updated until the end of a process. Variables are immediately updated. Xilinx recommends using signals for hardware descriptions; however, variables allow quick simulation.

If several values are assigned to a signal in one process, only the final value is used. When a value is assigned to a variable, the assignment takes place immediately. A variable maintains its value until a new value specified.

Signal:
Library IEEE;
use IEEE.std_logic_1164.all;
entity xor_sig is

port (A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC);
end xor_sig;

architecture SIG_ARCH of xor_sig is
signal D: STD_LOGIC;
begin
SIG:process (A,B,C)
begin
D <= A; — ignored !!
X <= C xor D;
D <= B; — overrides !!
Y <= C xor D;
end process;
end SIG_ARCH;

Variable:
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity xor_var is
port (A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC);
end xor_var;

architecture VAR_ARCH of xor_var is
begin

VAR:process (A,B,C)
variable D: STD_LOGIC;
begin
D := A;
X <= C xor D;
D := B;
Y <= C xor D;
end process;
end VAR_ARCH;

Useful links:

1. http://www.xilinx.com/itp/xilinx4/data/docs/sim/coding4.html
2. http://www.gmvhdl.com/signals.htm