Xilinx vs Altera
I have problems comparing gate number for FPGA implementation using Xilinx with implementation using Altera. They use different building blocks. Xilinx uses terms like slices LUT (Look Up Table),FF (Flip Flop) and LC (Logic Cell) while Altera uses LE (Logic Elements).
Here said that the logic cell to logic element ratio is 1.125:1, despite generally similar functionality. Therefore, divide Xilinx’s stated LC count by 1.125 to get the equivalent Altera LE count. More details here.
This site mentions that:
Xilinx: 1 slices = 2 LUT + 2 FF + some more logic
Altera: 1 LE = 1 LUT + 1FF + some more logic
So 1 slice (xilinx) = 2 LE (altera).