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  • CG 4:47 pm on November 17, 2010 Permalink | Reply
    Tags: , , , , tristate buffer,   

    LUT and Tristate buffer 


    library ieee;
    use ieee.std_logic_1164.all;

    entity lutmulCGver2 is
    port (
    clk : in std_logic;
    e : in std_logic;
    r : in std_logic;
    a, b: in std_logic_vector(3 downto 0);
    c: out std_logic_vector(3 downto 0);
    i, j, k : out std_logic_vector(3 downto 0);
    enA, enB, enC : in std_logic
    );
    end entity lutmulCGver2;

    architecture behavioral of lutmulCGver2 is
    -- signal i : integer range 0 to 6:=0;
    -- signal j : integer range 0 to 6:=0;
    signal tribus : std_logic_vector ( 3 downto 0 );
    signal enable : std_logic:='0';
    type alog is array (0 to 2**3 - 2) of std_logic_vector(3 downto 0);
    constant my_alog : alog := (
    0 => "0001",
    1 => "0010",
    2 => "0100",
    3 => "0011",
    4 => "0110",
    5 => "1111",
    6 => "0101");

    type log is array (1 to 2**3 - 1) of std_logic_vector(3 downto 0);
    -- type log is array (1 to 2**3 - 1) of integer;
    constant my_log : log := (
    1 => "0000",
    2 => "0001",
    3 => "0011",
    4 => "0010",
    5 => "0110",
    6 => "0100",
    7 => "0101");

    begin

    process(enA, enB, a, b)
    begin
    if enA = '1' then
    tribus <= a;
    elsif enB = '1' then
    tribus <= b;
    else
    tribus <= "ZZZZ";
    end if;
    end process;

    process(enC)
    begin
    if enC = '1' then
    c <= "0000";
    end case;
    end if;
    -- k <= (i xor j) xor "1011"; -- xor untuk mereduksi, tapi hanya
    berlaku untuk kalau generatornya x atau x+1
    end process;
    end architecture behavioral;

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    • Budi Rahardjo 4:59 pm on November 17, 2010 Permalink | Reply

      good stuff (sambil belum dibaca tea :))

      • CG 5:08 pm on November 17, 2010 Permalink | Reply

        halah, padahal mau nanya, udah bener belum waveformsnya?

  • CG 6:22 pm on November 2, 2010 Permalink | Reply
    Tags: , , tristate buffer,   

    More tristate buffer 


    library IEEE;
    use IEEE.STD_LOGIC_1164.all;

    entity tristate is
    generic( width : integer := 7 );
    port ( enA, enB, enC : in std_logic;
    A, B: in std_logic_vector( width downto 0);
    C : out std_logic_vector( width downto 0)
    );
    end tristate;

    architecture rtl of tristate is
    signal tribus : std_logic_vector ( width downto 0 );
    begin
    process(enA, enB, A, B)
    begin
    if enA = '1' then
    tribus <= A;
    elsif enB = '1' then
    tribus <= B;
    else
    tribus <= "ZZZZZZZZ";
    end if;

    end process;

    process(enC)
    begin
    if enC = '1' then
    C <= tribus;
    end if;
    end process;
    end rtl;

     
  • CG 9:55 pm on October 29, 2010 Permalink | Reply
    Tags: , , , tristate buffer,   

    Tristate buffer 


    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;

    ENTITY bidir IS
    PORT(
    bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
    oe, clk : IN STD_LOGIC;
    inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    outp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
    END bidir;

    ARCHITECTURE maxpld OF bidir IS
    SIGNAL a : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores
    -- value from input.
    SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores
    BEGIN -- feedback value.
    PROCESS(clk)
    BEGIN
    IF clk = '1' AND clk'EVENT THEN -- Creates the flipflops
    a <= inp;
    outp <= b;
    END IF;
    END PROCESS;
    PROCESS (oe, bidir) -- Behavioral representation
    BEGIN -- of tri-states.
    IF( oe = '0') THEN
    bidir <= "ZZZZZZZZ";
    b <= bidir;
    ELSE
    bidir <= a;
    b <= bidir;
    END IF;
    END PROCESS;
    END maxpld;

     

     
    • Budi Rahardjo 12:11 am on October 30, 2010 Permalink | Reply

      Ok I can see that the tri-state is happening. Try this approach with your design and see if it can utilize tri-state in sharing the look-up table.

      • CG 5:51 am on October 30, 2010 Permalink | Reply

        haih, bikin tri-state aja susah gini ya 😀

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